NI PXI-5122/5142 and NI PXIe-5122 Clocking
- Updated2023-09-20
- 4 minute(s) read
NI PXI-5122/5142 and NI PXIe-5122 Clocking
The clock circuitry on the NI PXI-5122/5142 and the NI PXIe-5122 offer versatile clocking options with the ability to use either the internal 100 MHz sample clock or to accept an external sample clock that you provide. You can also use the phase-locked loop (PLL) circuit on these digitizers to phase lock the internal 100 MHz sample clock with the PXI 10 MHz reference or with an external reference clock that you provide. The following diagram shows the clocking options of these digitizers.
Sample Clock
The sample clock is sent to the ADC of each channel and to the input timing engine. The digitizers can decimate their sample clocks (internal or external) by an integer divisor. When using an external clock, you can use decimation to achieve rates below the external clock frequency.
Internal Sample Clock
These digitizers have an onboard voltage controlled crystal oscillator (VCXO) running at 100 MHz. When using the onboard 100 MHz oscillator, you can choose either free-run mode or PLL mode. In free-run mode, the sample clock is the calibrated 100 MHz frequency of the VCXO. In PLL mode, the device phase locks its 100 MHz sample clock to the supplied reference clock. The PLL mode is useful when synchronizing the digitizer with other devices in a measurement system.
External Sample Clock
Some applications may require sampling at specific intervals that cannot be achieved by using the internal 100 MHz clock. In these cases these digitizers can accept an external sample clock. External clocking also provides a method to synchronize the digitizer to other devices in a measurement system by distributing a common clock to multiple devices. An external sample clock can be supplied to the digitizer from the front panel connector or by routing the signal on the PXI backplane over the PXI star trigger line. Refer to the hardware specifications document for external sample clock requirements.
Reference Clock
The reference clock is used in the digitizer's phase-locked loop (PLL) circuit to synchronize the sample clock to the reference clock. The digitizers can accept a reference clock from the front panel (CLK IN) as well as from PXI_CLK10. This reference clock can be any frequency from 5 MHz to 20 MHz (in 1 MHz increments) if it is provided to CLK IN. The PXI_CLK10 is always a 10 MHz clock. The frequency stability of the sample clock matches that of the PLL reference clock when the two are phase locked. In turn, phase locking synchronizes clocks of multiple devices that are phase locked to the same reference clock. The default setting for the reference clock is None, or not to use a reference clock.
Exporting Sample Clock
To achieve sampling rates other than 100 MS/s when using the internal sample clock, the digitizer decimates the sampled data. When you set a sampling rate of 50 MS/s, the NI PXI-5122/5142 can only store one out of every two samples received from the ADCs to onboard memory. They can sample at rates of 100/n MS/s, where n is an integer value between 1 and 216. Because the digitizer does not change the frequency of the clock sent to the ADCs, it creates a sample clock for export based on the effective sampling rate that you have configured. When sampling at the maximum rate, a free-running version of the actual sample clock is exported to the front panel of the digitizer. When the data is being decimated, a divided down version of the sample clock is exported. The divided down version of the sample clock only toggles while data is being acquired, and is driven low after the acquisition completes.
Exporting Reference Clock
If you are using an external reference clock to phase lock the internal sample clock, you can export the reference clock for use with other instruments. For more information on exporting the reference clock, refer to the NI PXI-5122/5124/5142 and NI PXIe-5122 Routing Matrix.