NI PXIe-5114 Clocking

The clock circuitry on the NI PXIe-5114 offers versatile clocking options with its ability to use either the internal 250 MHz sample clock or to accept an external sample clock that you provide. You can also use the phase-locked loop (PLL) circuit on the NI PXIe-5114 to phase lock the internal 250 MHz sample clock with the PXI 10 MHz reference or with an external reference clock that you provide. The following diagram shows the clocking options of the NI PXIe-5114.


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Sample Clock

The sample clock is sent to the ADC of each channel and to the input timing engine. The NI PXIe-5114 can decimate its sample clock (internal or external) by an integer divisor. When using an external clock, you can use decimation to achieve rates below the external clock frequency.

Internal Sample Clock

The NI PXIe-5114 has an onboard voltage controlled crystal oscillator (VCXO) running at 250 MHz. When using the onboard 250 MHz oscillator, you can choose either free-run mode or PLL mode. In free-run mode, the sample clock is the calibrated 250 MHz frequency of the VCXO. In PLL mode, the NI PXIe-5114 phase locks its 250 MHz sample clock to the supplied reference clock. The PLL mode is useful when synchronizing the NI PXIe-5114 with other devices in a measurement system.

External Sample Clock

Some applications may require sampling at specific intervals that cannot be achieved by using the internal 250 MHz clock. In these cases the NI PXIe-5114 can accept an external sample clock. External clocking also provides a method to synchronize the NI PXIe-5114 to other devices in a measurement system by distributing a common clock to multiple devices. An external sample clock can be supplied to the NI PXIe-5114 from the front panel connector or by routing the signal on the PXI backplane over the PXI star trigger line. Refer to the NI PXI/PXIe/PCI-5114 Specifications document that shipped with the device for external sample clock requirements.

Note   When you use an external sample clock, the TDC is disabled. Refer to the NI PXI/PXIe/PCI-5114 Specifications for information on how this affects trigger holdoff and trigger resolution.

Reference Clock

The reference clock is used in the NI PXIe-5114 phase-locked loop (PLL) circuit to synchronize the sample clock to the reference clock. The NI PXIe-5114 can accept a reference clock from its front panel (CLK IN) as well as from PXI_CLK10. This reference clock can be any frequency from 5 MHz to 20 MHz (in 1 MHz increments) if it is provided to CLK IN. The PXI_CLK10 is always a 10 MHz clock. The frequency stability of the sample clock matches that of the PLL reference clock when the two are phase locked. In turn, phase locking synchronizes clocks of multiple devices that are phase locked to the same reference clock. The default setting for the NI PXIe-5114 reference clock is None, or no reference clock is used.

Note   Locking to a reference clock is not valid when using an external sample clock.

Exporting Reference Clock

If you are using an external reference clock to phase lock the internal sample clock, you can export the reference clock for use with other instruments. For more information on exporting the reference clock, refer to the NI PXIe-5114 Routing Matrix.