PXIe-2739 Block Diagram

Figure 1. PXIe-2739 Block Diagram

PXIe-2739 Block Diagram

The diagram above shows the entire PXIe-2739 assembly. Relays are split between a daughterboard and a motherboard. The voltage isolation on the PXIe-2739 is provided by the relays and an isolation transformer for the relay resistive self-test circuitry.

The PXIe-2739 uses the DIN160 connector for the front panel, which allows the use of common cable accessories.

Relays and Relay Drivers

The PXIe-2739 uses 256 non-latching DPDT relays to implement a 16x16 crosspoint 2 wire matrix. Refer to PXIe-2739 Topology for more details.

The relay drivers in the PXIe-2739 can control 8 relays each and have a serial interface. The field-programmable gate array (FPGA) drives the serial interface to each of these drivers.

The FPGA also provides access to a flash memory that stores relay counts. The PXIe-2739 uses armature relays, and the relay operation count tracking is enabled as it is critical to preventative maintenance.

The power budget in the PXIe-2739 is controlled by the software, and the PXIe-2739 is able to drive up to 90 relays simultaneously before exceeding the maximum amount of available current on the internal relay driver power rail.

Resistive Self-Test

The PXIe-2739's self-test feature is based on an isolated high-voltage section. This section contains a reference resistor and multiplexing relays to connect the transformer to the relay rows and columns to be tested. The relay impedance is reflected through the transformer to the measurement circuit on the low-voltage side of the board.

You can use the NI Switch Health Center application to obtain the resistance of each individual relay on the PXIe-2739. The NI Switch Health Center calculates the resistance by measuring the total resistance of different combinations of signal paths.

Temperature Sensor

The temperature sensor in the PXIe-2739 has a serial interface which is read by the PXIe interface ASIC and provides the ability to monitor the motherboard temperature.

Clocking

The motherboard is clocked from the PXIe CLK100 provided by the backplane. The PXIe CLK 100 is buffered and then routed to both the FPGA and PXIe Interface ASIC.