10 MHz Input Reference

Several options are available to synchronize the system to an external clock:

  • Drive a clock from an external source through the PXI_CLK10_IN pin on the System Timing Slot.
  • Drive a clock from an external source through the 10 MHz REF IN SMA on the rear of the chassis (Timing and Synchronization upgrade only).
  • Connect a high-density trigger cable from the Trig Port 1/10 MHz Ref Out port of another chassis to the Trig Port 0/10 MHz REF IN port of this chassis (Timing and Synchronization upgrade only).

When an external clock is detected on any of these inputs, the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and distributes these signals to the slots. Refer to the PXIe-1092 Specifications for the specification information for an external clock provided on the PXI_CLK10_IN pin of the system timing slot or rear panel SMA.

If an external clock is present on more than one of these inputs, the signal is selected according to the following table.

Table 3. Backplane External Clock Input Truth Table
System Timing Slot PXI_CLK10_10 Rear 10 MHz REF IN SMA Connector Trig Port 0/ 10 MHz REF IN Port Backplane PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100
10 MHz clock present — — Phase-locked to System Timing Slot PXI_CLK10_IN
No clock present 10 MHz clock present — Phase-locked to Rear 10 MHz REF IN SMA
No clock present No clock present 10 MHz clock present Phase-locked to Trig Port 0/ 10 MHz REF IN Port
No clock present No clock present No clock present Backplane generates its own clocks. If the chassis has the Timing and Synchronization upgrade, the clocks are phase-locked to the OCXO.