PXI-5152 Specifications
- Updated2023-02-18
- 13 minute(s) read
PXI-5152 Specifications
Definitions
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty. Warranted specifications account for measurement uncertainties, temperature drift, and aging. Warranted specifications are ensured by design or verified during production and calibration.
Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
- Typical specifications describe the performance met by a majority of models.
- Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.
- Measured specifications describe the measured performance of a representative model.
Specifications in this document are Typical unless otherwise noted.
Conditions
Specifications are valid under the following conditions unless otherwise noted.
- All filter settings
- All impedance selections
- Sample clock set to 1 GS/s
- Real-Time Interleaved Sampling (TIS) mode provides a 2 GS/s real-time sample rate for a single channel
- The module is warmed up for 15 minutes at ambient temperature
- Calibration cycle is maintained
- The PXI/PCI chassis fan speed is set to HIGH, the foam fan filters are removed if present, and the empty slots contain chassis slot blockers and filler panels. For more information about cooling, refer to the Maintain Forced-Air Cooling Note to Users.
Vertical
Analog Input (Channel 0 and Channel 1)
Number of channels | Two (simultaneously sampled) |
Connectors | BNC |
Impedance and Coupling
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Input coupling | Software-selectable: AC, DC, GND |
Voltage Levels
Range (Vpk-pk) | 50 Ω Offset (V) | 1 MΩ Offset (V) |
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0.1 | ±1 | ±1 |
0.2 | ||
0.4 | ||
1 | ||
2 | ±6 | ±10 |
4 | ±5 | |
10 | ±2 |
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Accuracy
Resolution | 8 bits | ||||||||||||||||||
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Programmable vertical offset accuracy[2] | ±0.9% of offset setting, warranted | ||||||||||||||||||
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Bandwidth and Transient Response
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Bandwidth limit filter | 20 MHz noise filter | ||||||||||||||||||
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Spectral Characteristics
Noise
Range (Vpk-pk) | Noise Filter On | Noise Filter Off |
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0.1 | 240 µVrms (0.24% FS) | 320 µVrms (0.32% FS) |
0.2 | 480 µVrms (0.24% FS) | 600 µVrms (0.30% FS) |
0.4 | 960 µVrms (0.24% FS) | 1.12 mVrms (0.28% FS) |
1 | 2.4 mVrms (0.24% FS) | 2.6 mVrms (0.26% FS) |
2 | 4.8 mVrms (0.24% FS) | 6.0 mVrms (0.30% FS) |
4 | 9.6 mVrms (0.24% FS) | 11.2 mVrms (0.28% FS) |
10 | 24 mVrms (0.24% FS) | 26 mVrms (0.26% FS) |
Channel-to-channel skew | <100 ps |
Horizontal
Sample Clock
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Onboard Clock (Internal VCSO)
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Sample clock delay range | ±1 Sample clock period | ||||||||
Sample clock delay/adjustment resolution | ≤5 ps |
External Sample Clock
Sources | PFI 0 (front panel SMB connector) |
Frequency range[18] | 350 MHz to 1 GHz |
Duty cycle tolerance | 45% to 55% |
Phase-Locked Loop (PLL) Reference Clock
Sources | PXI_CLK10 (PXI backplane connector) PFI 0 (front panel SMB connector) |
Frequency range[19] | 5 MHz to 20 MHz in 1 MHz increments Default: 10 MHz |
Duty cycle tolerance | 45% to 55% |
Exported Reference Clock destinations | PXI_Trig <0..7> (backplane connector) PFI 1 (front panel SMB connector) |
Sample Clock and Reference Clock Input (PFI 0, Front Panel Connector)
Input voltage range | Sine wave: 0.65 Vpk-pk to 2.8 Vpk-pk (0 dBm to 13 dBm) |
Maximum input overload | 7 V RMS with |Peaks| ≤10 V |
Impedance | 50 Ω |
Coupling | AC |
Reference Clock Output (PFI 1, Front Panel Connector)
Output impedance | 50 Ω |
Logic type | 3.3 V CMOS, except when exporting 5 V |
Maximum drive current | ±24 mA |
Trigger
Trigger types[20] | Edge Window Hysteresis Video Digital Immediate Software | ||||||||
Trigger sources | CH 0 CH 1 TRIG PFI <0..1> PXI_Trig <0..6> PXI Star Trigger Software | ||||||||
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Holdoff | From ream time up to [(232 - 1) × Sample clock period] | ||||||||
Trigger delay | From 0 up to [(235 - 1) - Posttrigger Samples] × (1 / Sample Rate), in seconds |
Analog Trigger
Trigger types | Edge Window Hysteresis | ||||||
Sources | CH 0 (front panel BNC connector) CH 1 (front panel BNC connector) TRIG (front panel BNC connector) | ||||||
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Voltage resolution | 8 bits (1 in 256) | ||||||
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Trigger jitter[23] | ≤10 psrms, typical ≤20 psrms, maximum | ||||||
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Digital Trigger
Trigger type | Digital |
Sources | PXI_Trig <0..6> (backplane connector) PFI <0..1> (front panel SMB connectors) PXI Star Trigger (backplane connector) |
External Trigger Input (Front Panel Connector)
Connector | BNC |
Impedance | 1 MΩ in parallel with a nominal capacitance of 22 pF |
Coupling | AC, DC |
AC coupling cutoff (-3 dB) | 12 Hz |
Input voltage range | ±5 V |
Maximum input overload | |Peaks| ≤42 V |
PFI 0 and PFI 1 (Programmable Function Interface, Front Panel Connectors)
Connector | SMB jack |
Direction | Bidirectional |
As an Input (Trigger)
Destination | Start trigger (acquisition arm) Reference (stop) trigger Arm reference trigger Advance trigger |
Input impedance | 150 kΩ, nominal |
VIH | 2.0 V |
VIL | 0.8 V |
Maximum input overload | -0.5 V to 5.5 V |
Maximum frequency | 25 MHz |
As an Output (Event)
Sources | Start trigger (acquisition arm) Reference (stop) trigger End of record Done (end of acquisition) Probe compensation[24] |
Output impedance | 50 Ω |
Logic type | 3.3 V CMOS |
Maximum drive current | ±24 mA |
Maximum frequency | 25 MHz |
Waveform Specifications
Real-Time and RIS Modes | Real-Time TIS Mode |
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8 MB standard (8 MS) per channel | 8 MB standard (8 MS) |
64 MB option (64 MS) per channel | 64 MB option (64 MS) |
256 MB option (256 MS) per channel | 256 MB option (256 MS) |
512 MB option (512 MS) per channel | 512 MB option (512 MS) |
Minimum record length | 1 sample | ||||||||||
Number of pretrigger samples | Zero up to full record length | ||||||||||
Number of posttrigger samples | Zero up to full record length | ||||||||||
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Allocated onboard memory per record | [(Record length × 1 byte/sample) + 400 bytes] rounded up to next multiple of 128 bytes |
Calibration
External Calibration
External calibration calibrates the VCSO and the voltage reference. All calibration constants are stored in nonvolatile memory.
Self-Calibration
Self-calibration is done on software command. The calibration corrects for gain, offset, triggering, and timing errors for all input ranges.
Calibration Specifications
Interval for external calibration | 2 years |
Warm-up time[27] | 15 minutes |
Software
Driver Software
Driver support for the PXI-5152 was first available in NI-SCOPE 3.2.
NI-SCOPE is an IVI-compliant driver that allows you to configure, control, and calibrate the PXI-5152. NI-SCOPE provides application programming interfaces for many development environments.
Application Software
NI-SCOPE provides programming interfaces, documentation, and examples for the following application development environments:
- LabVIEW
- LabWindows™/CVI™
- Measurement Studio
- Microsoft Visual C/C++
- .NET (C# and VB.NET)
Interactive Soft Front Panel and Configuration
When you install NI-SCOPE on a 64-bit system, you can monitor, control, and record measurements from the PXI-5152 using InstrumentStudio.
InstrumentStudio is a software-based front panel application that allows you to perform interactive measurements on several different device types in a single program.
Interactive control of the PXI-5152 was first available via InstrumentStudio in NI-SCOPE and via the NI-SCOPE SFP in NI-SCOPE3.2. InstrumentStudio and the NI-SCOPE SFP are included on the NI-SCOPE media.
NI Measurement & Automation Explorer (MAX) also provides interactive configuration and test tools for the PXI-5152. MAX is included on the driver media.
TClk Specifications
You can use the NI TClk synchronization method and the NI-TClk driver to align the Sample clocks on any number of supported devices, in one or more chassis. For more information about TClk synchronization, refer to the NI-TClk Synchronization Help, which is located within the NI High-Speed Digitizers Help. For other configurations, including multichassis systems, contact NI Technical Support at ni.com/support.
Intermodule SMC Synchronization Using NI-TClk for Identical Modules
Synchronization specifications are valid under the following conditions:
- All modules are installed in one NI PXI-1042 chassis
- The NI-TClk driver is used to align the Sample clocks of each module.
- All parameters are set to identical values for each module.
- Modules are synchronized without using an external Sample clock.
- Sample clock set to 1 GS/s and all filters are disabled.
Skew[28] | 500 ps |
Skew after manual adjustment | ≤5 ps |
Sample clock delay/adjustment resolution | ≤5 ps |
Power
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Total power | 21.65 W |
Physical
Dimensions | 3U, one-slot, PXI module 21.6 cm × 2.0 cm × 13.0 cm (8.5 in × 0.8 in × 5.1 in) |
Weight | 462 g (16.3 oz) |
Environment
Environment
Maximum altitude | 2,000 m (at 25 °C ambient temperature) |
Pollution Degree | 2 |
Indoor use only.
Operating Environment
Ambient temperature range | 0 °C to 55 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.) |
Relative humidity range | 10% to 90%, noncondensing (Tested in accordance with IEC 60068-2-56.) |
Storage Environment
Ambient temperature range | -40 °C to 71 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.) |
Relative humidity range | 5% to 95%, noncondensing (Tested in accordance with IEC 60068-2-56.) |
Shock and Vibration
Operational shock | 30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Test profile developed in accordance with MIL-PRF-28800F.) | ||||||
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Compliance and Certifications
Safety Compliance Standards
This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:
- IEC 61010-1, EN 61010-1
- UL 61010-1, CSA C22.2 No. 61010-1
Electromagnetic Compatibility
- EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
- EN 55011 (CISPR 11): Group 1, Class A emissions
- EN 55022 (CISPR 22): Class A emissions
- EN 55024 (CISPR 24): Immunity
- AS/NZS CISPR 11: Group 1, Class A emissions
- AS/NZS CISPR 22: Class A emissions
- FCC 47 CFR Part 15B: Class A emissions
- ICES-001: Class A emissions
Product Certifications and Declarations
Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for NI products, visit ni.com/product-certifications, search by model number, and click the appropriate link.
Environmental Management
NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.
For additional environmental information, refer to the Engineering a Healthy Planet web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.
EU and UK Customers
电子信息产品污染控制管理办法(中国RoHS)
1 Programmable vertical offset = 0 V.
2 Within ±5 °C of self-calibration temperature.
3 Use DC drift to calculate errors when temperature changes more than ±5 °C since the last self-calibration.
4 Measured on one channel with test signal applied to another channel, with same range setting on both channels.
5 10 V signal applied to external trigger channel. Applies to all ranges on CH 0 and CH 1.
6 Bandwidth for 0 to 30 °C. Reduce by 0.25% per °C above 30 °C for all input ranges. Filter off for all input ranges.
7 Normalized to 51 kHz.
8 Filter off.
9 50 Ω terminator connected to front panel BNC connector.
10 50 Ω source assumed.
11 1 V input range, 10 MHz, -1 dBFS input signal. Includes the 2nd through the 5th harmonics.
12 50 Ω terminator connected to input.
13 Internal Sample clock is locked to the Reference clock or derived from the onboard VCSO.
14 Divide by n decimation used for all rates less than 1 GS/s.
15 TIS is a type of real-time sampling that is sometimes called ping-pong.
16 RIS is a type of equivalent-time sampling.
17 Refer to your chassis specifications for the Reference clock accuracy.
18 Divide by n decimation available where 1 ≤ n ≤ 65,535. For more information about the Sample clock and decimation, refer to the NI High-Speed Digitizers Help.
19 The PLL Reference clock frequency must be accurate to ±50 ppm.
20 Refer to the following sources and the NI High-Speed Digitizers Help for more information about which sources are available for each trigger type.
21 Holdoff set to 0. Onboard Sample clock at maximum rate.
22 DC to 300 MHz.
23 Within ±5 °C of self-calibration temperature.
24 1 kHz, 50% duty cycle square wave. PFI 1 only.
25 Single-record mode and multiple-record mode.
26 It is possible to exceed these numbers if you fetch records while acquiring data. For more information, refer to the High-Speed Digitizers Help.
28 Caused by clock and analog path delay differences. No manual adjustment performed.