Disconnect Clock Terminals

Closes a route between a source clock terminal and a destination clock terminal.

Inputs/Outputs

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session in

The session that you obtain from Initialize.

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error in

Error conditions that occur before this node runs.

The node responds to this input according to standard error behavior.

Standard Error Behavior

Default value: No error

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source terminal

The source clock terminal of the clock you would like to connect.

PXI_Clk10 The 10 MHz backplane clock of the PXI or PXIe chassis.
ClkIn The ClkIn input connector on the front panel of your device.
Oscillator The oscillator of the device specified in the instrument handle terminal.
DDS Clock The DDS signal generated by the device specified in the instrument handle terminal.
PFI_LVDS<n> The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of the module.
PXIe_DStarC<n> The differential star trigger line of the PXIe chassis. Use DStarC lines to route clock and/or trigger signals from a peripheral slot to a system timing slot.
Note Each PXIe_DStarC trigger is mapped to a single slot. This mapping is vendor-specific. Refer to the chassis' documentation for more information on the mapping of differential star trigger lines.
PXIe_DStarA The differential star trigger line of the PXIe chassis. Use DStarA lines to route clock signals from a system timing slot to a peripheral slot.
Note Each PXIe_DStarA trigger is mapped to a single slot. This mapping is vendor specific. Refer to the chassis' documentation for more information on the mapping of differential star trigger lines.
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destination terminal

The destination clock terminal to which the source terminal connects.

PXI_Clk10_In The connector pin used to provide the backplane with a reference 10 MHz signal from the system timing slot. When you connect a signal to this pin, PXI_Clk10 and PXIe_Clk100 are phase-aligned to this reference.
ClkOut The ClkOut connector on the front panel of the module.
BoardClk The timekeeper used to schedule future time events and timestamping on certain modules. BoardClk accepts a 10 MHz reference clock and multiples it by 10 to create a 100 MHz clock for use as a timekeeper.
Note BoardClk is a valid terminal only on PXI-668x devices.
PFI_LVDS<n> The PFI_LVDS output connector on the front panel of your device.
PXIe_DStarA<n> The differential star trigger line of the PXIe chassis. Use DStarA lines to route clock signals from a system timing slot to a peripheral slot.
Note Each PXIe_DStarA trigger is mapped to a single slot. This mapping is vendor specific. Refer to the chassis' documentation for more information on the mapping of differential star trigger lines.
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session out

The session handle for the NI-Sync device. Pass this handle to other NI-Sync nodes to program the behavior of the device.

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error out

Error information.

The node produces this output according to standard error behavior.

Standard Error Behavior