Digital Filtering Considerations for C Series Devices or or TestScale Modules
- Updated2024-10-22
- 3 minute(s) read
Digital Filtering Considerations for C Series Devices or or TestScale Modules
For C Series devices or or TestScale Modules, you can filter digital I/O lines and digital input signals.
Timing and Triggering Filters for Digital I/O Lines
You can configure digital filters on the device by choosing three fixed values (112.5 nS, 6.4 µS, 2.56 mS) or a custom filter value. The custom filter value must be the same for all lines across the device. For example, if you choose a filter value of 2 µS for PFI 0, any other filterable line on the device can only choose from the three fixed values and the 2 µs value selected for the custom filter. For each digital line or input terminal, there are four attributes/properties associated with these digital filters: Digital Filter Enable, Digital Filter Minimum Pulse Width, Digital Filter Timebase Source, and Digital Filter Timebase Rate.
When you set the Digital Filter Enable to true, you must also configure the Digital Filter Minimum Pulse Width attribute/property. When you select a filter value with the Digital Filter Minimum Pulse Width attribute/property, the device uses an internal 32-bit utility counter to generate the desired filter value. If you would like to generate the filter clock using your own external signal, you can use the Digital Filter Timebase Source and Digital Filter Timebase Rate attributes/properties. You must configure both to use an external signal as the source for the digital filter. The Digital Filter Minimum Pulse Width attribute/property represents the minimum value that is guaranteed to be passed into the device. The maximum pulse width guaranteed to be blocked by the device is one filter clock tick smaller than the minimum pulse width guaranteed to pass the filter.
The following table lists the attributes/properties for terminals that can be digitally filtered.
Type | Attribute/Property |
---|---|
Channel | Frequency Input Terminal |
Period Input Terminal | |
Count Edges Input Terminal | |
Count Edges Count Direction | |
Position A Input Terminal | |
Position B Input Terminal | |
Position Z Input Terminal | |
Pulse Input Terminal (Time, Ticks, and Frequency) | |
Pulse Width Input Terminal | |
Two-Edge First Input Terminal | |
Two-Edge Second Input Terminal | |
Semi-Period Input Terminal | |
Counter Input Timebase Source (External Only) | |
Counter Output Timebase Source (External Only) | |
Timing | Sample Clock Source |
Triggering | Arm Start Digital Edge Source |
Pause Analog Level Source | |
Pause Analog Window Source | |
Pause Digital Level Source | |
Reference Analog Edge Source | |
Reference Analog Window Source | |
Reference Digital Edge Source | |
Start Analog Edge Source | |
Start Analog Window Source | |
Start Digital Edge Source |
Filters for Digital Input Signals
Filters are also available on digital input lines, such as cDAQ1Mod1/port0/line0, but the filters do not support the fixed values mentioned previously or external timebase sources. The minimum filter pulse width for digital input lines is 50 nS and can be set in increments of 25 nS. All digital input lines on a module must use the same minimum filter pulse width. The maximum pulse width guaranteed to be rejected by the filter is half the pulse width guaranteed to pass the filter.
This filtering circuitry exists on the chassis and is available for all digital lines that exist on parallel digital modules. With a parallel digital module, input or output data is communicated in parallel between the module and the chassis backplane rather than being communicated serially.
Parallel Digital Input Modules for C Series Devices and TestScale Modules
- NI 9344
- NI 9401
- NI 9402
- NI 9411
- NI 9421
- NI 9422
- NI 9423
- NI 9435
- NI 9436
- NI 9437
- TS-15050 DIO P0