PCIe-785x Base Clocks

A base clock is a digital signal existing in hardware that you can use as a clock for an FPGA application. The following figure shows the clock routing for the PCIe-785x base clocks.

The PCIe-785x provides several base clock resources that can be used to run a LabVIEW FPGA VI. The 40 MHz onboard clock is generated within the device FPGA using a PLL. The PLL source is the onboard 100 MHz oscillator clock.

The following base clock resources are available for your device.

DRAM Clock

DRAM Clock uses the 100 MHz Oscillator as its source. This clock drives the DRAM interface. This clock is not available on the PCIe-7856.

40 MHz Onboard Clock

The 40 MHz Onboard Clock is the default clock in your LabVIEW FPGA project. This clock can be used as a top-level clock for running your LabVIEW FPGA VI.

External Clock x

An External Clock is input only and can be used as a clock source for a Single Cycle Timed Loop (SCTL) to run at the frequency of your choice. The recommended input frequency range is 1 MHz to 80 MHz. An External Clock cannot be used as a Top-Level clock. The source for an External Clock input must be from a stable and glitch-free clock source. There is one External Clock on Connector 1.