Timed Loop

The FPGA Module single-cycle Timed Loop differs from the standard LabVIEW Timed Loop in that the timing of the FPGA single-cycle Timed Loop corresponds exactly to the clock rate of the FPGA clock you specify. By configuring a single-cycle Timed Loop to use a clock other than the base clock of the FPGA target, you can implement multiple clock domains in an FPGA VI. You can specify the FPGA clock that controls the single-cycle Timed Loop by wiring a value to the Source Name input on the Input Node of the single-cycle Timed Loop or by using the Configure Timed Loop dialog box.

You cannot use the following VIs, functions, or structures in a single-cycle Timed Loop.

  • Analog Period Measurement VI
  • Butterworth Filter VI
  • Discrete Delay VI
  • Divide function
  • FIFO Clear function
  • FPGA I/O Method Node except with some FPGA targets
  • FPGA I/O Property Node except with some FPGA targets
  • Interrupt VI
  • Look-Up Table 1D VI with the Interpolate data checkbox selected
  • Loop Timer Express VI
  • Multiple FPGA I/O Nodes configured for the same I/O resource if at least one node is inside the loop and at least one node is outside the loop
  • Non-reentrant subVIs if you use multiple instances
  • Notch Filter VI
  • PID VI
  • Quotient & Remainder function
  • Reciprocal function
  • Rotate 1D Array function
  • Sine Wave Generator VI
  • Single-precision floating-point operations
  • Square Root function
  • Timed Loop
  • Wait Express VI
  • Wait on Occurrence function
  • While Loop
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    The FPGA target you use might not support additional VIs or functions. Also, some targets do not support specific I/O items both inside and outside a single-cycle Timed Loop. Refer to the specific FPGA target hardware documentation for more information.

    The following table describes how single-cycle Timed Loops interact with other components.

    Single-Cycle Timed Loops Open in VIs under My Computer If you place the single-cycle Timed Loop in a VI open under My Computer, the single-cycle Timed Loop displays some terminals that FPGA targets do not support. So, if you open the VI under an FPGA target, the unsupported terminals still appear. If you place the single-cycle Timed Loop in a VI open under an FPGA target, the single-cycle Timed Loop hides terminals that are not supported. So, if you open the VI under My Computer, the single-cycle Timed Loop does not display all terminals that My Computer supports.
    Single-Cycle Timed Loops Open in VIs under an FPGA Target When you place a single-cycle Timed Loop in an FPGA VI, only the Source Name input appears visible by default. Other than Source Name and Error, the inputs available on the Input Node of the single-cycle Timed Loop have no effect when you use the single-cycle Timed Loop in an FPGA VI. Error is the only supported output of the single-cycle Timed Loop in an FPGA VI.
    Note Do not add frames before or after the single-cycle Timed Loop frame to try to use the single-cycle Timed Loop as a Timed Sequence structure in an FPGA VI. The LabVIEW FPGA Module does not support Timed Sequence structures.
    Indicators in Single-Cycle Timed Loops You can place indicators in the single-cycle Timed Loop only if you do not have any local variables writing to the indicators.
    FPGA I/O Nodes and Single-Cycle Timed Loops You can use the FPGA I/O Node in the single-cycle Timed Loop if the FPGA target supports it. If the FPGA target you use supports the single-cycle Timed Loop, you can use only the Arbitrate if Multiple Requestors Only and Never Arbitrate arbitration options. If you select Arbitrate if Multiple Requestors Only, you cannot use more than one instance of the FPGA I/O Node for a specific I/O item in the FPGA VI. If you select Never Arbitrate, you can use more than one instance of the FPGA I/O Node for a specific I/O item in the FPGA VI if each instance is in a single-cycle Timed Loop executing at the same rate.
    Flat Sequences and Single-Cycle Timed Loops You can use the Flat Sequence or Stacked Sequence structure in the single-cycle Timed Loop. However, all sequence frames execute in one clock cycle.
    SubVIs and Single-Cycle Timed Loops You cannot use more than one instance of a non-reentrant or shared subVI in a single-cycle Timed Loop. You can use multiple instances of a reentrant VI inside a single-cycle Timed Loop as long as the reentrant VI does not use shared resources.
    Wait On Occurrence Function and Single-Cycle Timed Loops You cannot use the Wait on Occurrence function in a single-cycle Timed Loop. However, you can use the Set Occurrence function. You then can use the Wait on Occurrence function outside the single-cycle Timed Loop in a While Loop or For Loop.
    One Clock Cycle Functions, Internal Registers, and Single-Cycle Timed Loops You can use some functions in the single-cycle Timed Loop that take one clock cycle to execute, such as the Memory Method Node. If you use this function to read from a memory item that uses embedded block memory, the output of this function is not valid until the next iteration of the single-cycle Timed Loop. Therefore, you must wire the outputs of such functions directly to uninitialized shift registers.
    Note Functions such as the Memory Method Node, FFT Express VI, and FPGA I/O, have internal registers that can appear as paths in the Timing Violation Analysis window.
    Arrays and Clusters in Single-Cycle Timed Loops You can compile FPGA VIs with arrays and clusters wired to certain Numeric and Boolean functions inside the single-cycle Timed Loop.
    For Loops in Single-Cycle Timed Loops You can place a For Loop in a single-cycle Timed Loop if the For Loop contains only Array, Numeric, Boolean, or Comparison operations and uses only auto-indexed tunnels. Objects that generate or contain state, such as shift registers, Feedback Nodes, or VI calls, are not allowed in For Loops within a single-cycle Timed Loop.
    Single-Precision Floating-Point (SGL) Data Type and Single-Cycle Timed Loops Most functions cannot perform single-precision floating-point operations inside a single-cycle Timed Loop because they require more than one clock cycle to execute but they do not have handshaking signals.