Interleave 1D Arrays

Interleaves corresponding elements from the input arrays into a single output array.


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Inputs/Outputs

  • c1ddbl.png array —

    array 0..n-1 must be 1D. If the input array is not the same size, the number of elements in interleaved array equals the number of elements in the smallest input array multiplied by the number of input arrays.

  • c1ddbl.png array —

  • i1ddbl.png interleaved array —

    interleaved array[0] contains array 0[0], interleaved array[1] contains array 1[0], interleaved array[n-1] contains array n-1[0], interleaved array[n] contains array 0[1], and so on, where n is the number of input terminals.

    The following table shows how elements from the input arrays affect interleaved array.

    array 0array 1array 2interleaved array
    [0, 3][1, 4][2, 5][0, 1, 2, 3, 4, 5]
    [0, 3, 5][1][2, 4][0, 1, 2]

    • FPGA Module Details

    The following details apply when you use this object in an FPGA VI.

    Note The following details are subject to change with each version of the LabVIEW FPGA Module.
    Single-Cycle Timed Loop Supported.
    Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. You can use constant or non-constant inputs.
    Timing This function requires no clock cycles to execute because it does not include an internal register.
    Resources This function consumes no FPGA resources because it is purely a wiring operation.