Overview

Use reference designs to customize the LabVIEW harness around the simulation model IP that is imported through the IP to FPGA Conversion Utility and HDL Coder Support Package for NI FPGA Hardware. With reference designs, you can customize to support additional NI FPGA hardware, leverage other hardware and CPU interfaces, configure additional properties, add other LabVIEW FPGA processing to the same bitfile, and more.

Creating and Customizing the Template Reference Project

You can use the create-template command from ip2fpgaCLI.exe to create a new template project. For example, ip2fpgaCLI.exe create-template –t PXIe-7971R –o C:\Users\Test\Documents creates a new template project targeting the PXIe-7971R.

After creating the reference project, add any desired structure to support different BoardIOs, VI-Registers, and other customization to the project and TopLevel.vi. Any created BoardIO or VI-Registers are placed in TopLevel.vi automatically during project generation, based on the BoardCustomization.json.

To create internal I/Os that you can link to model ports, such as DMA FIFOs, MGT interfaces, etc., create controls and indicators with a label that begins with "IO."

You can use FlexRIO adapter modules within a custom reference design. After creating the template, add the IO module to the project, then use the desired IO from that module in TopLevel.vi.

After creating the reference design project, create the BoardCustomization.json file based on the added customization. Refer to Guidelines for BoardCustomization.json for more details.

Guidelines for BoardCustomization.json

Create a BoardCustomization.json to add new hardware support with customizations to describe how simulation model ports connect to BoardIO in a custom reference design project.

Json Structure

• ProjectPath: Path to a custom reference design project (if applicable).
• TopLevelVI: Path to the TopLevelVI leveraged for this hardware. Two TopLevelVIs are shipped with the tool, but you can create a new one if developing a Reference Design project.
  • For R-series targets: "TopLevelVI": "..\TemplatePrjs\TopLevel.vi"
  • For FlexRIO multifunction targets: "TopLevelVI": "..\TemplatePrjs\PXIe-789x\TopLevel.vi"
• TargetType: Provide the target module name.
• BoardIOData: The json core portion. This structure provides input to ip2fpgaCLI.exe regarding the FPGA IO nodes present on the target and how to connect them to the simulation model ports.
  • Name: The pin name, which you can specify by an exact value (that is, “Name”: “Connector0/DIO0”) or with a loop component variable (that is, “Name”: “Connector0/AI$i”).
  • Direction: The BoardIO’s directions, specified as Input or Output.
  • LoopComponent: Allows grouping similar pins together.
  • Datatype: The LabVIEW BoardIO datatype. Supported values are:
    • Boolean
    • SGL
    • I8, I16, I32, I64
    • U8, U16, U32, U64
    • FXP<+/-,27,5>
    • FXP<+,27,5>
  • StructureLabel: The structure name where you should place the BoardIO (that is, “StructureLabel”: “AI Read Loop”). If the LoopComponent is configured, all pins referenced are linked to the same structure. Supported structures are:
    • WhileLoop
    • TimedLoop
    • ForLoop
    • FlatSequence
    • CaseStructure
  • Args: Arguments for supported structures. The supported arguments are:
    • FlatSequence >> Frame: Frame number (that is, “Args”: “Frame:0”).
    • CaseStructure >> Frame: State name (that is, “Args”: “Frame:True”).
  • InvokeNodes: You can script invoke nodes for BoardIOs into structures. The argument formats are:
    • PropertyName: Name of the invoke node property.
    • ParentStructure: The StructureLabel for the invoke node.
    • StructureArgs: Any arguments for the structure, if applicable.
      • Parameters: Name: Input parameter name.
      • DataType: Datatype of the parameter (Boolean, U8, U16, U32, I8, I16, I32).
      • Value: Constant value connected to the node parameter.
  • PropertyNodes: You can script property nodes for BoardIOs into structures. The supported arguments are:
    • ParentStructure: The property node StructureLabel.
    • StructureArgs: Any arguments for the structure, if applicable.
    • Parameters:
      • Name: Input parameter name.
      • DataType: The parameter datatype (Boolean, U8, U16, U32, I8, I16, I32).
      • Value: Constant value connected to the node parameter.

Registering Reference Designs and Adding New Hardware in HDL Coder

Adding New Targets to HDL Coder Support Package for NI FPGA Hardware

After creating a BoardCustomization.json for a given hardware module, move the json to C:\Program Files\National Instruments\IP to FPGA Conversion Utility\LVComponents\config data.

After moving the file, open Generate Plugin Board for Matlab.vi in C:\Program Files\National Instruments\IP to FPGA Conversion Utility\PluginBoardGenerationTool. Within the VI, specify the BoardCustomization Folder Path (the folder that contains the created BoardCustomization.json files), the Output Folder Path (where the HDL coder-related files will be generated), and the FPGA Category Options (select the target related category which the BoardCustomization.json).

After generating the files, add the generated folder specified in the Output Folder Path to the MATLAB path via the Set Path command.

Registering Custom Reference Designs for HDL Coder Support Package for NI FPGA Hardware

Create a plugin_rd by referencing the default plugin_rd.m in \+{Target}\+ReferenceDesign. Add that plugin_rd.m to a new folder with the desired referenced design name (that is, “\+{Target}\+TestRefDesign”).

Modify hdlcoder_ref_design_customization.m to add the plugin_rd reference design plugin created in addition to the default one that is already listed. For example,

rd = {

'PXIe7971R.ReferenceDesign.plugin_rd', ...

'PXIe7971R.TestDesign.plugin_rd'

};

All registered hardware and reference designs are now discoverable in steps 1.1 and 1.2 of the HDL Workflow Advisor.