NI-Sync Limitations on Linux Desktop and NI Linux Real-Time
Updated Apr 25, 2023
Overview
In some cases, features discussed in the NI-Sync documentation are unavailable on either Linux Desktop or NI Linux Real-Time. This document should be used to understand the limitations of NI-Sync when working on these platforms.
The following graphical utilities are not available:
LabVIEW Express VIs
The Measurement and Automation Explorer (MAX) graphical configuration utility
Soft front panels
Linux Desktop only: NI-Sync only provides development support for LabVIEW 64-bit and C/C++/ANSI C. See the NI-Sync ReadMe for information on what versions are supported. See the version specific NI-Sync Help for more information on which properties are supported.
Note: NI-Sync for Linux RT accepts case insensitive terminal names
Error codes returned when route creation is not possible may differ between Linux Desktop and Linux RT driver versions. This is generated by the fact that the two drivers use different routing coordinators.
Example: NISYNC_ERROR_DEST_TERMINAL_IN_USE vs. NISYNC_ERROR_SRC_TERMINAL_INVALID. The error codes are still related to routing, but they are reported differently depending on the driver used.
Linux RT: The following parameters throw an invalid parameter error if assigned negative values (whereas on Windows, these would have undefined behavior).
NISYNC_ATTR_OSCILLATOR_VOLTAGE
NISYNC_ATTR_CLK10_PHASE_ADJUST
NISYNC_ATTR_DDS_PHASE_ADJUST
NISYNC_ATTR_DDS_VCXO_VOLTAGE
Routing through DStarA Network: There are some terminals that can be connected either through DStarA network or through FPGA. These terminal pairs are (DStarC to LVDS) and (LVDS to LVDS)
Linux RT:nisync_ConnectClkTerminals tries to route the signal through DStarA network if possible. It fallsback to using the FPGA.
Linux RT: nisync_ConnectTriggerTerminals tries to route the signal through FPGA if possible. It fallsback to using DStarA network.
Comparatively, on PharLAP/Windows:
DStarC to LVDS is routed through DStarA network (with no fallback) if the route is async and not inverted (clock routes are always async and not inverted); otherwise it is always routed through FPGA.