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The SDLC Toolkit for LabVIEW with Clock Recovery is a software add-on that provides a library containing FPGA VIs for data transmission (TX) and reception (RX). This add-on supports standard encoding, as well as embedded clock recovery. The add-on provides a LabVIEW FPGA Driver Library containing two FPGA VIs; single-channel or multichannel data communication can be implemented with additional drivers. You can use the VIs to implement cyclic redundancy check (CRC) calculation, forward error correction, and bit stuffing or unstuffing on the FPGA. Additionally, the SDLC Toolkit for LabVIEW with Clock Recovery supports a data rate range from 110 baud to 10 Mbaud with a configurable baud rate.