Interpreting Common Xilinx Compilation Errors in the LabVIEW FPGA Module

When compiling code for FPGA devices where designs can take long amounts of time to complete, errors resulting in failed compilations can be frustrating. Sometimes simply recompiling can solve the problem, while other situations may require significant design optimizations to succeed. When improvements and code changes are needed an understanding of how the errors relate back to the initial design can greatly streamline the necessary troubleshooting. This document covers many common errors that you may encounter when compiling FPGA code. For each error, a brief description and troubleshooting suggestions are provided. While not all possible compilation errors are covered, many common errors will report similar issues or follow the same troubleshooting process. For more specific details on recommendations in this document, refer to the LabVIEW Help or the Additional Resources section at the end of this document.

Once a compilation has been started, you can check the status and results of the compilation in the Compilation Status Window. If the compilation has failed, the Summary report will display the errors and other details. You can also view the Xilinx log for a detailed report, including the errors listed. You can save the log for future reference by clicking Save when viewing the Xilinx log report.

Note: It is normal to get several warnings in the Xilinx logs - even in successful compilations. You can ignore the warnings when identifying areas to troubleshoot. Focus on specific errors first, and only worry about warnings if they are known to be a problem for other reasons.

The following are common Xilinx error codes that can be thrown due to resource limitations when you compile your LabVIEW FPGA design:

These errors generally indicate that the design requires more physical resources to implement than are available on the FPGA. You may see that estimated usages are within acceptable levels despite the errors, so it can be difficult to determine areas to focus on. The following are general tips that can help you compile your projects successfully if you encounter a resource limitation:

• Adjust the build settings to optimize for area (Note: this may increase compilation times, and may result in performance trade-offs).
• Optimize your code. Try the following best practices and optimization techniques within your LabVIEW FPGA code.
  • Reduce the amount of logic in the VI
  • Reduce the number of multiplications, FIFOs, and/or amount of memory on the block diagram
  • Reduce the number of objects on the front panel
  • Change arbitration settings
  • Use Timed Loops instead of other loops
  • Use Timed Loops for resource-intensive sections of the block diagram that do not require any looping

LabVIEW FPGA will typically catch timing errors and populate them to users in the Timing Violation Analysis Window as opposed to specific compilation errors. This window will appear any time a compilation fails due to timing violations in LabVIEW FPGA code, and will list out each code path that failed timing. Double-clicking on items in each path will take you directly to the block diagram component responsible.

The following are suggestions for improving timing in your FPGA code:

• Adjust the build settings to optimize for performance (Note: this may increase compilation times, and may result in area trade-offs).
• Optimize your code. Try the following best practices and optimization techniques within your LabVIEW FPGA code.
  • Reduce the amount of logic in the VI
  • Add pipelining to increase parallelism
  • Use Timed Loops instead of other loops
  • Change arbitration settings

Sometimes the compilation window displays the following message instead of a specific error: "LabVIEW FPGA: Some of the compilation steps were not executed." This message is indicative of many different problems and requires narrowing down the behavior to determine the exact problem. Some common causes of this behavior are crashes of the Xilinx compiler tool due to a lack of memory, or a loss of the connection with the compiler by LabVIEW FPGA. 

To narrow down the issue, try the following troubleshooting steps:

• Monitor your PC’s memory usage during the compilation, or check the Xilinx logs for memory usage. If memory usage is too high or your system runs out of memory, consider trying a system with more resources.
• If you upgraded to Windows 10 (version 1709) after installing the LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2, check the NI Update Service for critical updates. For more information, see the LabVIEW 2018 FPGA Module Known Issues List or contact NI Support.
• Refer to the Xilinx website at www.xilinx.com for memory requirements of different FPGA targets. Failure to meet the target-specific memory requirement may result in unpredictable compilation results. Note that the required memory documented by Xilinx is defined for a single compilation and will increase proportionately as the number of parallel compilations increases. To approximate the required memory for N parallel compilations, multiply N by the Xilinx memory requirements.
• Try using the NI LabVIEW FPGA Compile Cloud Service instead of your local compiler.
• Compile a blank VI on your system.
• Compile on a different PC to rule out any installation issues.
• Reduce array logic in your FPGA code, or replace arrays with BlockRAM Memory implementations.
• Contact  NI Support.

The following table covers some of the other common errors you may encounter:

Here are some additional tips if you encounter the errors above, or other errors not listed in this document:

• Start with general design optimizations and try different compiler settings in the build specification.
• Isolate sections of code that could have a higher probability for issues. Items such as external IP, CLIP, or similar may require special attention to configuration or have unexpected compatibility issues.
• Research the error through Xilinx resources, such as the official Xilinx website and help articles. Sometimes these can give more detailed explanations on the meaning behind the errors and how they could be related to the general architecture of your design.
• Search for the particular error in NI's KnowledgeBase articles and in the FPGA Module Known Issues List for the version of LabVIEW FPGA you are using.
• Contact NI support.

Additional Resources

• Compatibility between Xilinx Compilation Tools and NI FPGA Hardware
• Slices on an FPGA Chip
• FPGA Fundamentals 
• The NI LabVIEW High-Performance FPGA Developer's Guide
• How Can I Optimize FPGA Resource Usage or Speed?
• LabVIEW FPGA Module Help: Optimizing FPGA VIs for Speed and Size