Framegrabber Specifications for the NI Camera File Generator

Updated Mar 10, 2020

Overview

This document provides the framegrabber specifications needed when using the NI Camera File Generator.

Introduction
Timing Signal Requirements
Tap Configurations
Additional Resources

Introduction

The specifications for your camera must be compatible with an NI framegrabber. The specifications for each NI framegrabber are indicated in the following table. Timing signal requirements and tap configurations are also listed below.

	PCI/PXI 1422	PCI/PXI 1424	PCI 1426	PCIe 1427	PCI/PXI 1428	PCIe 1429	PCIe 1430	PCIe 1433	PXIe 1435	PCIe 1437
Electrical Standard	LVDS /RS-644, RS-422	LVDS /RS-644, RS-422, TTL	Camera Link	Camera Link	Camera Link	Camera Link	Camera Link	Camera Link	Camera Link	Camera Link
Pixel Clock Frequency	Up to 40 MHz	Up to 40 MHz	Up to 50 MHz	Up to 80 MHz	Up to 50 MHz	Up to 85 MHz	Up to 85 MHz	Up to 85 MHz	Up to 85 MHz	Up to 85 MHz
Data Width	Up to 16 bits	Up to 32 bits	Up to 24 bits	Up to 24 bits	Up to 32 bits	Up to 80 bits¹	Up to 24 bits	Up to 80 bits	Up to 80 bits	Up to 80 bits

¹ PCIe 1429 supports 10 tap acquisition (up to 8 bits per tap) for a pixel clock rate of 67 MHz or less.

Timing Signal Requirements

A camera must meet the following timing signal requirements to be supported by a framegrabber. The Line Enable and Frame Enable signals must be active for all valid pixels.

Timing Signal Requirements	PCI/PXI-1422, PCI/PXI-1424, PCI-1426, PCI/PXI 1428	PCIe-1427, PCIe-1429, PCIe-1430, PCIe-1433, PXIe-1435,PCIe-1437
Time for Line Enable (LVAL) - Time between Lines	At Least 4 Pixel Clock Counts	At Least 1 Pixel Clock Count
Time for Frame Enable (FVAL) - Time Between Frames	At Least 100 Pixel Clock Counts	At Least 20 Pixel Clock Counts
Blank Lines Between Frames	At Least 4 Lines Between Signals (or Use Non-Continuous Enable)	None

Tap Configurations

A tap is defined as a channel of data from the camera. A camera with a one-pixel output on each clock is referred to as a 1 tap camera. Some cameras output multiple pixels on the same pixel clock. If a camera outputs two pixels on the same pixel clock, it is a 2 tap camera.

The tap configuration of your camera is an important factor to consider when choosing a compatible framegrabber because the device must be able to support the pixel depth of your camera multiplied by the number of taps. Pixel depth is measured in bits.

NI framegrabbers have a data bus that is divided into 8-bit ports. Each port can hold up to 8 bits of image data. If the pixel depth of a camera is greater than 8 bits, the pixel will require the use of more than one port. Each pixel must be aligned to a port boundary.

*Note: The PCIe 1429 supports 10 tap acquisition (up to 8 bits per tap) for a pixel clock rate of 67 MHz or less.

Additional Resources

Number of Taps	Bit Depth	PCI/PXI 1422	PCI/PXI 1424	PCI 1426	PCIe 1427	PCI/PXI 1428	PCIe 1429	PCIe 1430	PCIe 1433	PXIe 1435	PCIe 1437
1 Tap	8 bit
	10 bit
	12 bit
	14 bit
	16 bit
	24 bit RGB
2 Tap	8 bit
	10 bit
	12 bit
	14 bit
	16 bit
	24 bit RGB
4 Tap	8 bit
	10 bit
	12 bit
	14 bit
	16 bit
	24 bit RGB
8 Tap	8 bit
	10 bit
	12 bit
	14 bit
	16 bit
	24 bit RGB
10 Tap	8 bit
	10 bit
	12 bit
	14 bit
	16 bit
	24 bit RGB

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