This sample project is based on the Simple State Machine and Queued Message Handler templates. Refer to the Simple State Machine and Queued Message Handler templates and their documentation, available from the Create Project dialog box, for information about how these templates work.
This sample project is designed for an NI cRIO-9074 with the following components:
This sample project consists of nine parallel loops across three execution targets. The following loops run in parallel on the desktop computer:
The following loops run in parallel on the real-time controller:
The following loops run in parallel on the FPGA:
General sequence of steps:
The FPGA VI in this sample project is compiled for specific FPGA and I/O hardware. If you have a different FPGA or different C Series modules, you must adapt this sample project to your hardware. The following steps refer to NI CompactRIO devices, but you also can adapt this sample project to an NI Single-Board RIO device.
Locate the Control (PID) subdiagram of the Case Structure in FPGA Main.vi and modify this subdiagram to apply a control algorithm. This sample project is designed to implement a PID algorithm. By default, this algorithm returns a constant value of 0 on all output channels. You can perform a different algorithm on each individual channel
Modify the Safe State, Default subdiagram of the Case structure in FPGA Main.vi to write safe values to the output channels. The values you write here should be ones that you know the connected hardware can safely handle. By default, this subdiagram writes a value of 0 to all output channels.
This subdiagram executes in the following situations:
In the Project Explorer window, open My Computer»Globals»Global - Configuration Options.vi. Use this VI to configure the following settings: