Archived: Designing Semiconductor ATE With the NI PXIe-6556 Digital ATE Module

The NI PXIe-6556 integrates with a device under test (DUT) and other instrumentation through interfaces. Figure 1 shows a connectivity pinout. You can access the primary digital I/O through a VHDCI connector. There is a second VHDCI connector for remote sense lines. Also, the front of the module features three SMA connectors for importing an external clock as well as driving an external clock and a PFI connector. You can program the programmable functional interface (PFI) in software to be an input or output as well as to have it define itself as a clock or trigger-based port. Figure 1 shows PFI4 as a DDC 52clock and PFI5 as a strobe.

Figure 1. NI PXIe-6556 High-Density Connector Pinout

NI offers several options for interfacing to VHDCI and PFI lines. You can achieve direct connectivity through the SHC68-C68-D4 cable, which is a shielded 50 Ω cable designed to preserve signal quality through impedance matching and minimal crosstalk. NI provides these cables in lengths ranging from 0.5 m to 2 m. Both ends of the cable use a VHDCI interface. To simplify interfacing to a printed circuit board (PCB), NI offers PCB-mountable connectors. Different connector blocks are available with a screw terminal (CB-2162) or a single-ended SMB breakout (SMB-2163). If you wish to directly connect to header pins from the NI PXIe-6556, you can choose the cable option with integrated flying leads called the SHC68-H1X38 cable. Some example NI connectivity options are shown in Figure 2.

Figure 2. NI Digital and Analog I/O Connectivity Options

Connectivity solutions are ideal for characterization or development applications when you typically make only a few connections. When you need repeatable and fast connectivity to the NI PXIe-6556, a mass interconnect solution is ideal. This is common for automated test equipment in manufacturing. Although beyond the scope of this paper, with mass interconnectivity, you get the correct DUT platform while ensuring good connectivity and easy digital I/O hardware module accessibility.

NI works closely with MAC panel and Virginia Panel. Both of these vendors offer several connectivity solutions. Figure 3 illustrates connectivity from a DUT to a PXI system.

Figure 3. Mass Interconnect Solution to a PXI System With the SCOUT MAC Panel Interface

Figure 4. Actual Rack and Connectivity to a Virginia Panel Mass Interconnect

Digital patterns are composed of both digital states (such as 0, 1, Z) and timing information. Although you have many ways to represent these digital patterns, as long as the digital states and timing information are identical, the resulting digital pattern will also be identical. This, of course, does not mean all digital test equipment is capable of generating these patterns because each tester has its own features and limitations; however, ignoring tester-specific limitations, you have multiple ways to represent a digital pattern. Consider the pattern in Figure 5:

Figure 5. Digital Pattern Timing Diagram

If you represent this digital pattern as a timing set and digital data, tset1 could be defined as

Given the above definition for tset1, the digital data could be defined as a list of vectors or as a scan chain.

Instead of using timing sets, you could oversample the data and specify that the pattern run at a certain rate. For the above pattern, sampling once every 50 ns (20 MHz) reconstructs the waveform without having to modify signal timing. Assuming a clock rate of 20 MHz, the digital pattern could be represented as

As stated above, all of these methods represent the same digital pattern shown in Figure 5. Again, this does not imply that all testers can generate this pattern; rather, you can use several methods to represent a digital pattern.

To further understand NI PXIe-6556 capabilities, consider the following timeplates taken from a WGL file:

For those not familiar with the timing definition of a WGL file,

D = Logic 0  S = Apply pattern data  x = Mask output (don’t care)   Q = Expect pattern data  

Although the NI PXIe-6556 does not support timing sets, as discussed above, you can use oversampling and deep onboard memory to represent the digital vectors. The first step when oversampling a pattern is to determine the desired clock rate. For best resource utilization, you should use the lowest clock rate that meets your needs. For tp1, each output transitions at X*(5 ns) + C, where X is an integer and C is a constant offset for each output channel. The same is true for the input channels because each transitions at X*(5 ns) + C, and, again, C is a constant value for each input channel.

Because all channels are a multiple of 5 ns plus an offset, you can set the clock rate to 1/(5 ns) or 200 MHz. To achieve the offset, C value, you need to configure the position delay to the appropriate value. Delay values are shown in the chart below.

¹The WGL file defines signal direction from a device perspective. The NI cards define a signal direction from a board perspective. This means that HSDIO naming is the opposite of the WGL file (input maps to generation and output to acquisition).

Applying the delay values above, the NI PXIe-6556 can generate any pattern using the tp1 timeplate.

Achieving a 100 ns Timeplate Period
Because the onboard clock is running at 200 MHz, each NI PXIe-6556 sample is output for 5 ns. To build a pattern that is 100 ns long, you need 20 samples. Thus, each vector defined in the WGL file is represented by 20 samples on the NI PXIe-6556.

Implementing Timing Sets for the GPIO Lines
As stated above, each sample lasts 5 ns and each WGL file vector is represented by 20 samples. Taking this and the delay chart from above into account, the following table shows the values of the 20 samples needed to compose a vector from the WGL file for each of the GPIO lines.

¹ The NI PXIe-6556 can drive 0, 1, and Z logic. The D states should be replaced by the values as defined in the digital vectors.
² The NI PXIe-6556 can drive 0, 1, and Z logic. The P state should be replaced by the previous value as defined in the digital vectors.
³ The NI PXIe-6556 can compare with L, H, and X states. The Q states should be replaced by the values defined in the digital vectors.

To show that this timing set has been implemented correctly, examine GPIO_3. When the NI PXIe-6556 is generating data, the logic changes after one period (5 ns) and holds the current value for the remaining 95 ns. This is the same as the timeplate defined in the WGL file. When comparing data, the NI PXIe-6556 ignores all data except the 11th and 12th samples. Keeping in mind the acquisition has been delayed 1 ns, this value is compared at 11*(5 ns) + (1 ns) or 56 ns, and again at 12*(5 ns) + (1 ns) or 61 ns. At all other times, 0 ns through 56 ns and 66 ns through 100 ns, the value is an X as defined by the timeplate.

Now suppose a digital pattern uses tp2. You could go through the same process as tp1. Determining the onboard clock rate (1/7.8125 ns) or 128 MHz would be a good selection. Because every value is a multiple of 7.8125 ns, no offset is needed. Using four samples, you can build any of the patterns defined in the WGL file.

What would happen if the WGL file contains vectors using both the tp1 and tp2 timeplates? If you run the tp2 patterns with the configuration from tp1, the effective time plate would be

Notice that the period and many of the edges are different from the original values. Although some applications are immune to this change, assume this behavior is unacceptable and try to improve pattern timing.

Ideally, you could increase the onboard clock rate and achieve the resolution you need to accurately represent the two timeplates. In the above case, this is not practical because the NI PXIe-6556 has a 200 MHz maximum clock rate.

Because increasing the clock rate is not an option, you could reconfigure the hardware when switching from tp1 to tp2, and vice versa. The hardware is capable of holding the last value while it is reconfigured. As long as the application and DUT can tolerate a few milliseconds of delay while the hardware is reconfigured, this is a good option.

If the application cannot tolerate a few milliseconds of delay, or if the application switches between tp1 and tp2 often, you could adjust the delay from sample clock rising edge value to split the difference between the two timing sets. Although this is not as accurate as reconfiguring the hardware, it is a good way to increase the accuracy.

Assuming it is acceptable to coerce tp2 to a 30 ns period, you could achieve an edge placement accuracy of ±860 ps. If the application allows all of the tp2 values to be scaled from 32 to 33.3 MHz (30 ns period), you can run patterns using either timing set without further timing adjustments or board reconfiguration.

For those accustomed to specifying timing sets, oversampling may seem like a foreign concept; however, most people do not need to get into the low-level details of oversampling data. You can use converters to change digital data in one format to another format with little input.

With the abundance of software tools and production test platforms, you can store digital data in a variety of files including the following:

• WGL (.wgl)
• STIL (.stil)
• VCD (.vcd)
• EVCD (.evcd)
• Teradyne (.atp)
• Advantest (.pin, .tim, .tmap, .pat)
• Verigy (.avc, .dvc)
• LTX (.evo, .eva)

You can group these files into one of two categories, the first being files generated from simulation (WGL, STIL, VCD, and EVCD). Which file format you use depends on the tools and packages the design engineer used. Keep in mind, the designer may have the option to save the data into more than one format.

The second category of files contains tester-specific files, such as .atp. Often, these files are built from converting or importing data from the simulation files discussed above. However, the data is not required to originate from simulation files. Sometimes, the test plan calls for reading and writing registers using a specific protocol. In this case, you can generate the files with the assistance of a script, or possibly generate them manually.

Although you have tools that can convert files from one tester format to another, you should generally use the original source file(s) to generate tester-specific files. All testers have limitations, and to run a particular pattern on a tester, you may need to make timing adjustments. When moving from one tester to another, you may need to change the adjusted timing again, which causes a file to be created that best represents the previous tester file. The best representation of the previous tester file may not be the best representation of the original file. Keeping this in mind, NI supports the conversion of several simulation files.

WGL/STIL

The Test System Strategies Incorporated (TSSI) TD-Scan tool is used throughout the semiconductor industry to convert both simulation files and test files to specific tester formats. For NI products, you can use the TD-Scan tool to convert both STIL and WGL files. When converting STIL or WGL files, you can adjust timing sets as shown in Figure 2, and then convert the STIL or WGL files to an ASCII-based format that NI products can easily use. For more information on the TD-Scan tool, read the Using TD-Scan With NI High-Speed Digital Devices white paper. 

Figure 6. TD-Scan Timing Editor Image

VCD

Using the NI Digital Waveform Editor, you can import VCD files. A GUI guides you through the process. First, select the type of signals (drive, compare, and/or bidirectional), as shown in Figure 3. When using bidirectional signals, the next step is to select the output enable signals and link them to the appropriate bidirectional signals. This is required because VCD does not contain signal direction information. Newer formats such as WGL and EVCD do not require this step.

Figure 7. VCD Import Wizard Signal Selection Step

Once you have linked the bidirectional signals, select a sampling rate and, if desired, override certain digital states. After setup is complete, the VCD file is imported into the NI Digital Waveform Editor, where you can save it and use it with NI high-speed digital I/O devices, including the NI PXIe-6556.

Although many testers can test a particular device, test engineers are rarely able to connect to the DUT and make all of the patterns work perfectly on the first try. To uncover the root cause of issues, test engineers need debug tools. Below are some of the debug tools that you can use with the NI PXIe-6556.

Pattern Analysis and Modification

With the NI Digital Waveform Editor, you can view and modify digital patterns. Figure 8 shows an image of the Digital Waveform Editor.

Figure 8. NI Digital Waveform Editor

Hardware Compare

With hardware compare, you can generate H, L, and X states. If the incoming signal is not as expected (for example, acquire “0” but generated “H”), a sample error occurs. If a sample error occurs, the NI PXIe-6556 stores the failing channel, sample number, and (optionally) the number of times it occurred in a row. Figure 9 shows the data returned from a hardware compare.

Figure 9. Hardware Compare Data

Acquired Data

You can always read the acquired digital data and analyze it through a test program, or save it to disk and analyze it using the Digital Waveform Editor. Figure 10 shows acquired digital data in LabVIEW.

Figure 10. LabVIEW Acquired Digital Data

Custom Debug Tools

Using NI software, you can create your own debug tools. Figure 11 shows a Shmoo plot created in LabVIEW.

Figure 11. LabVIEW Shmoo Plot

When you need to expand the number of digital channels for test, you can add modules to the PXI chassis. Depending on the number of channels and the chassis that you choose, you may need to expand beyond a single chassis into a multiple-chassis configuration. NI recommends the NI PXIe-1075 chassis for most ATE applications to accommodate mixed-signal test hardware. When using this 18-slot chassis, you have the capacity to add up to eight NI PXIe-6556 modules. The eight NI PXIe-6556 modules offer 224 total pin parametric measurement unit (PPMU) lines. For expansion beyond 224 channels, you can use NI MXI-Express technology to bridge between multiple chassis. Figure 12 shows an example of this expansion.

Figure 12. Multiple PXI Chassis Expansion

Once you have added multiple NI PXIe-6556 modules to a chassis, you may want to synchronize the timing of each module to make it operate as though it were a larger channel device. You can do so with NI-TClk technology. NI-TClk is a synchronization tool found in all SMC-based modular instrument products from NI, such as high-speed digital devices, digitizers, analog waveform generators, and RF instruments. It uses synchronization circuitry on each device to align the clock signal as precise as 40 ps of clock skew. Read more about NI-TClk technology in the NI T-Clock Technology for Timing and Synchronization of Modular Instruments white paper.

Figure 13 shows an example of how you can implement NI-TClk in LabVIEW for multiple NI PXIe-6556 modules.

Figure 13. LabVIEW Block Diagram Showing T-Clock Integration With Two Modules

Summary

The NI PXIe-6556 pin electronics card from NI offers flexible per pin digital test and measurement. You can interface it to various NI connectivity options for high-fidelity signal control and test. When you use the NI PXIe-6556 for manufacturing test, you have a variety of mass interconnectivity options from MAC Panel and Virginia Panel to choose from. The NI PXIe-6556 offers a flexible software interface supported in LabVIEW, .NET, and C. It does not work with fixed timing sets, but you can create these through oversampling techniques. These oversampling techniques use different methods of data delay and data skew so you can create your own custom timing sets. The NI PXIe-6556 imports and exports different common digital waveform formats such as WGL and STIL. NI uses TSSI software tools to implement some of the waveform conversions for compatibility with the digital waveform data types that work directly with the NI PXIe-6556. Once you have the waveform data type of interest, you may need to debug your digital waveform. In this case, the NI Digital Waveform Editor can help you visualize and debug the digital waveform patterns. You can also use LabVIEW waveform display functions so you can customize your view by creating graphs such as Shmoo plots. To integrate multiple NI PXIe-6556 modules, NI offers an NI-TClk function that manages a selected trigger delay to get 40 ps synchronization between modules. You can use MXI technology to bridge this NI-TClk capability to multiple chassis when you exceed the number of modules in a single chassis.