This document contains the NI VeriStand 2019 known issues that were discovered before and since the release of NI VeriStand 2019. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
The following items are known issues in VeriStand 2019 sorted by Date.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 402293 Return | Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN making it impossible to map to the channel correctly. Workaround: Use the channel mappings dialog to import from a text file instead of using the dialog.
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| 522678 Return | Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels When using the System Definition API to programmatically add an FPGA target to a System Definition file, the Parameters section typically included with PWM channels is excluded. Workaround: Add the FPGA manually to the System Definition via the System Explorer.
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| 372874 Return | Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names. When building a VI into a model for NI VeriStand, the build process will fail if any of the indicators or controls have identical names. Workaround: Use different names for the controls and indicators that will become the model's inports and outports.
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| 572887 Return | Setting the Frame Type option in the Raw Data Frame Configuration page has no effect. As the Frame Type is pulled from the XNET database, this System Definition setting does not affect the XNET configuration. Workaround: Set the Frame Type as desired in the XNET database. Do not use the Raw Data Frame Type Configuration option in the System Definition.
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| 468712 Return | VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device If Slow Background Conversion mode is enabled on a DAQ card (like a PXIe-4353) and it's the first DAQ device listed in the system definition, VeriStand incorrectly tries to use this device as the master timing card. VeriStand will do this even if there are other DAQ cards running without Slow Background Conversion enabled. Workaround: Add the DAQ card that you want to use as the master timing source to the system definition before adding the Slow Background Conversion DAQ card. If both cads are already in the system definition, remove and re-add the Slow Background Conversion-enabled card.
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| 672996 Return | Frequency channels for Counter Inputs read an incorrectly scaled value. The scaling on frequency channels with counter input modules is inaccurate. The channel value in VeriStand will depend on the number of frequency channels being read. Workaround: A customer scale can be applied that reads the correct value. This scale should be: Channel Value / (Number of frequency channels + 1)
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| 703891 Return | Cannot import LabVIEW model for Linux to VeriStand that has nested clusters as an inport. VeriStand cannot import a LabVIEW model for Linux if it has a nested cluster as an inport. Workaround: N/A
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| 720821 Return | System Definition File error using Inline Timing and Sync Custom Device When using Custom Device Template Tool to create an Inline Timing and Sync Custom Device, inporting that device creates a "Timing Source Init VI_1" section in the System Definition XML that is unnecessary and causes error -307832 when adding the Inline Timing and Sync Custom Device. Workaround: Open the VeriStand project's nivssdf with a text editor, and delete the "Timing Source Init VI_1" section.
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Document last updated on 7/19/2019
The following items are known issues in VeriStand 2019 sorted by Category.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| Miscellaneous | ||||||
| 672996 Return | Frequency channels for Counter Inputs read an incorrectly scaled value. The scaling on frequency channels with counter input modules is inaccurate. The channel value in VeriStand will depend on the number of frequency channels being read. Workaround: A customer scale can be applied that reads the correct value. This scale should be: Channel Value / (Number of frequency channels + 1)
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| 720821 Return | System Definition File error using Inline Timing and Sync Custom Device When using Custom Device Template Tool to create an Inline Timing and Sync Custom Device, inporting that device creates a "Timing Source Init VI_1" section in the System Definition XML that is unnecessary and causes error -307832 when adding the Inline Timing and Sync Custom Device. Workaround: Open the VeriStand project's nivssdf with a text editor, and delete the "Timing Source Init VI_1" section.
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| Model Interfacing | ||||||
| 703891 Return | Cannot import LabVIEW model for Linux to VeriStand that has nested clusters as an inport. VeriStand cannot import a LabVIEW model for Linux if it has a nested cluster as an inport. Workaround: N/A
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| 402293 Return | Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN Model files imported to VeriStand with vector channels appear as Nx1 rather than 1xN making it impossible to map to the channel correctly. Workaround: Use the channel mappings dialog to import from a text file instead of using the dialog.
| |||||
| 372874 Return | Building a LabVIEW model for NI VeriStand fails if the controls or indicators have identical names. When building a VI into a model for NI VeriStand, the build process will fail if any of the indicators or controls have identical names. Workaround: Use different names for the controls and indicators that will become the model's inports and outports.
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| Performance | ||||||
| System Explorer | ||||||
| 572887 Return | Setting the Frame Type option in the Raw Data Frame Configuration page has no effect. As the Frame Type is pulled from the XNET database, this System Definition setting does not affect the XNET configuration. Workaround: Set the Frame Type as desired in the XNET database. Do not use the Raw Data Frame Type Configuration option in the System Definition.
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| 468712 Return | VeriStand may select a DAQ card with Slow Background Conversion mode enabled as the chassis master timing device If Slow Background Conversion mode is enabled on a DAQ card (like a PXIe-4353) and it's the first DAQ device listed in the system definition, VeriStand incorrectly tries to use this device as the master timing card. VeriStand will do this even if there are other DAQ cards running without Slow Background Conversion enabled. Workaround: Add the DAQ card that you want to use as the master timing source to the system definition before adding the Slow Background Conversion DAQ card. If both cads are already in the system definition, remove and re-add the Slow Background Conversion-enabled card.
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| Using the API | ||||||
| 522678 Return | Adding an FPGA target to the System Definition via the API will fail to add the Parameters section of PWM channels When using the System Definition API to programmatically add an FPGA target to a System Definition file, the Parameters section typically included with PWM channels is excluded. Workaround: Add the FPGA manually to the System Definition via the System Explorer.
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Document last updated on 7/19/2019