NI CompactRIO Device Drivers May 2018 and R Series MultifunctionRIO May 2018 Known Issues

Compilation Failure when using NI 9775 and NI 923x in one FPGA I/O Node

When using one FPGA I/O Node with a NI 9775 module as the master timebase and an NI 923x module as a slave, FPGA compilation will fail with the error "LabVIEW FPGA: The compilation failed due to a Xilinx error." 

Workaround:

Separate into two FPGA I/O Nodes and use a software boolean or a hardware digital signal to trigger the nodes to execute.

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Analog Input Channels 6 & 7 on PXI Express NI-7861 and NI-7862 have swapped Voltage Range values

The Voltage Range values are swapped between analog input channel 6 and 7 on PXI Express NI-7861 and NI-7862 cards. As a result, analog input channels 6 and 7 will read values scaled with improper gain only when set to different Voltage Ranges.

Workaround:

Update to NI R Series Multifunction RIO June 2019 (19.1). 

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Host Memory Buffer Read on FPGA Can Return FIFO Data

When using a Host Memory Buffer and a Host to Target DMA FIFO simultaneously, the Host Memory Buffer's Retrieve method on FPGA can incorrectly return data sent by the FIFO. This does not affect the FIFO's data in any way.

Workaround: 

Manually implement arbitration between Host-to-Target-FIFOs and the Host Memory Buffer's Request / Retrieve methods.  

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After Windows 10 Update 1703, USBLAN Does Not Function

If you already have CompactRIO 18.0 or 18.1 installed prior to performing the Windows 10 1703 update ("Creators Update"), the USBLAN driver may stop functioning. The USBLAN driver is what CompactRIO uses to emulate an Ethernet port when you plug a RIO controller in via USB. With this issue, the USBLAN driver does not work and therefore Windows will not associate the RIO controller you plug in over USB. The device might show as "Generic Usb-EEM Network Adapter" in Windows Device Manager. If you did not have CompactRIO installed prior to the Windows update and install it afterward, you will not experience this issue. 

Workaround:  

See the KnowledgeBase Article: My Device Shows up as "Generic USB-EEM Network Adapter" in Device Manager. 

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Deploying an EtherCAT Master Changes the Programming Modes on cRIO-904x to Real-Time Scan

Deploying an EtherCAT master with a NI 9144 or NI 9145 slave containing C Series modules in Scan Mode will also change the corresponding C Series modules' program mode to Scan Mode on the local cRIO-904x chassis. If you have an existing FPGA application running on the cRIO-904x while deploying the EtherCAT master, the C Series' I/O Nodes will report error 65673 (if error terminals are enabled) and will hold the last reported value. You can confirm this is the issue you are experiencing by looking at the C Series modules in NI MAX and noting their programming mode has changed to "Real-Time Scan (I/O Variables)".

Workaround:

After deploying the chassis, you can use System Configuration functions to programmatically change the module's Programming Mode before starting the FPGA application. The general way to change programming modes programmatically is documented in this KnowledgeBase article, and a specific example (workaround_706379.zip) is attached to this document.  

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A firewall exception for the RIO Server is not configured for Windows cRIO-9081 or cRIO-9082

The RIO Server enables connections from remote LabVIEW applications to RIO devices on the local system. On Windows-based systems, a firewall exception for the RIO Server is not configured during the installation process of the driver. This can result in an inability to open FPGA Interface sessions to a CompactRIO 908x from remote Windows systems. Additionally, you won't be able to discover the chassis or modules of a CompactRIO 908x in a LabVIEW project. 

Workaround: 

Add a rule to the firewall allowing nirioserver.exe through it. 

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Cannot set modes for unavailable modules on NI cRIO-904x using the System Configuration API

If the module is not present in the NI cRIO-904x chassis, the user cannot set the mode of that module programmatically using the System Configuration API. This could impact a user attempting to replicate systems using the Replication and Deployment Utility. 

Workaround: 

Deploy the program to set the mode of an unknown module from the LabVIEW Project Explorer window. 

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Cannot access I/O variables remotely from modules with Japanese characters in the module name

The user cannot access I/O variables remotely from a module with Japanese characters in the module name. This is related to Issue #638899 where User Programs cannot be downloaded to the NI 9350 and the NI 9351. 

Workaround: 

Rename the module without using Japanese characters. 

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Analog input values read from the NI 9351 using Direct Access are incorrectly reported as 0.

The analog input channels AI0, AI1, AI2, and AI3 on the NI 9351 (Functional Safety module) will erroneously report a value of 0. This only occurs when using the Direct Access method to access the channels as opposed to the default Scanned Access. 

Workaround:

Use Scanned Access (which is the default access mode) to read channel values. 

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When using a partitionless SD card, the in-use LED will not illuminate on insertion of the SD card

When the entire SD card is formatted as FAT as opposed to formatting a partition of the SD card as FAT, the in-use LED will not illuminate upon insertion of the SD card. The SD card function will not be affected. 

Workaround:

Format the SD card with a FAT partition. 

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Zynq FPGA targets fail to format correctly occasionally after a firmware upgrade has been performed

After the firmware has been updated on a Zynq FPGA target, occasionally the target will not format correctly. This will manifest as a failed software installation. 

Workaround:

Manually reset the device and continue the software installation. 

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NI-MAX Database becomes corrupted after installing DAQmx if target is restarted too quickly following installation

After DAQmx is installed to a cRIO target, it requests a restart of the target. If the target is restarted too quickly following installation, the MXS database will become corrupted. This error will manifest as an inability to use any DAQmx Tasks or Scales or to configure DAQ devices.

Workaround:

Wait for a short period of time before restarting the target after installation. 

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Passthrough value on a digital output glitches when NI 9350 or NI 9351 is removed and reinserted in the backplane

When writing a  value via passthrough to a digital output, the output will glitch when the module is removed then reinserted into the backplane. The output will maintain its state when the module is removed but will toggle to the opposite state (i.e., TRUE will glitch to FALSE) when the module is reinserted.

Workaround:

No current workaround. 

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Touch screen input from at Touch Screen Monitor becomes increasingly inaccurate towards the edge of the Touch Screen Monitor

The touch screen input is precise when calibrating then becomes increasingly inaccurate as the pointer is moved towards the edge of the screen. The response is offset approximately one inch from the input point at the edge of the screen and elements near the edge cannot be interacted with.  This affects the TSM-1012, TSM-1015, and TSM-1017.

Workaround: 

Use a mouse instead of the touch screen input. 

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PXIe R Series Modules Do Not PLL to the PXIe_CLK100 Backplane

PXIe R Series modules do not automatically and cannot be forced to PLL to the PXIe_CLK100 backplane clock of the PXIe chassis they are seated in. PXIe R Series modules reference their internal clock and may drift from the backplane clock. Internal clocks on PXIe R Series modules have different performance specifications than PXIe_CLK100 and should not be relied upon for synchronization with other devices on the backplane.

Workaround:

Complete the following steps to force PXIe R Series modules to use the PXI_CLK10 clock, a 10 MHz clock that is phase locked to the PXIe_CLK100 backplane clock:

1. Right-click the R Series PXIe module FPGA target within the LabVIEW project window and select New >> FPGA Base Clock.
2. Choose the PXI Clk10 MHz Clock resource and click OK. This will make the 10 MHz PXI_CLK10 clock available as a base clock.
3. Right click the R Series PXIe module FPGA target and select Properties.
4. Within the properties, navigate to the Top-Level Clock category and select the PXI Clk10 MHz Clock.

The PXI_CLK10 clock is now set as the base clock for the FPGA target. The R Series module base clock no longer drifts from modules using PXIe_CLK100, and the base clock inherits the specifications defined by the PXIe chassis for PXI_CLK10.

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