| ID | Fixed Issue |
|---|---|
|
672108 |
Changing the connector for an R Series expansion chassis in the LabVIEW project after a previous compile caused the intermediate file generation of the next compile to fail. |
|
679827 |
Compilation would fail on cRIO targets (excluding cRIO-904X targets) when the bitfile included NI 985x FPGA IO Nodes. |
|
680529 |
On cRIO-904x targets, a pre-compilation error would occur when using a top-level clock of 120 MHz or greater for the NI 9770 or the NI 9775. |
|
682048 |
Host to Target and Target to Host DMA FIFOs on cRIO-906x, sbRIO-96x7, sbRIO-9651, NI 9147, NI 9149, NI 793x, roboRIO, and myRIO may have failed to report low-level bus errors. This may have resulted in stale data followed by a timeout error. |
|
680240 |
On certain RIO units and only at certain temperatures, a low-level bus error is thrown on startup that can cause DMA FIFOs to error (typically with error -52018). In certain cases, this could impact a running application (under issue #678603, and could affect RS-485 ports), although this has occurred much less frequently than the error on startup. This has been observed on cRIO-9068, and theoretically could impact other controllers using the same architecture (cRIO-906x, sbRIO-96x7, sbRIO-9651, NI 9147, NI 9149, NI 793x, roboRIO, and myRIO). This issue is related to #682048 on this same page, meaning that in cRIO 17.0 - 17.6 there may not be an error thrown. |
|
683399 |
Calling Open FPGA VI Reference.vi on a VxWorks-based controller would return error -63193 ("The requested feature is not supported.") when targeting the FPGA on a NI Linux RT device. |