NI CompactRIO Device Drivers and R Series MultifunctionRIO (May 2017) Known Issues

NI 9202 FPGA IO Nodes acquiring faster than maximum data rate

Adding an NI 9202 to a CompactRIO project without configuring the module properties or programmatically setting the data rate will cause the NI 9202 FPGA I/O Nodes to acquire data at a rate faster than the maximum data rate. This can lead to invalid data or the error 65539, but it is not the only cause of error 65539.

Workaround:

For more information on the workarounds listed below, see KnowledgeBase article "Error 65539 Using FPGA I/O Nodes with NI 9202."

• Right-click the module in the LabVIEW Project and select Properties. Configure the settings (if necessary) and click OK.
• Programmatically set the data rate in your LabVIEW FPGA VI.

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NI 9262 output does not update when using parallel FPGA I/O Nodes

When using multiple, parallel FPGA I/O Nodes with the NI 9262, the output values do not get updated from the first written output value. If the first written value is non-zero, this can cause the module to be unable to return to zero volt output.

Workaround:

• Write to all NI 9262 channels in one node. This is the same approach taken in the second option in the KnowledgeBase article "NI-9262 Channels Overwritten to 0 V".
• Update to CompactRIO Device Drivers October 2019 (19.5)

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NI 9262 FPGA I/O Nodes overwrite output to zero volts

When programming the NI 9262 in Calibrated mode using an FPGA I/O Node to set channel output values, any channels that are not included in the node are overwritten and set to output zero volts. This issue manifests itself when multiple FPGA I/O Nodes are used in a LabVIEW FPGA program, and will cause channels that were previously outputting non-zero values to be reset to zero. The issue does not affect users that are programming the module in Raw mode or with User-Controlled I/O Sampling.

Workaround: 

For more details on the listed workarounds, see the KnowledgeBase article "NI-9262 Channels Overwritten to 0 V".

• Use the module in Raw Calibration Mode
• Use User-Controlled I/O Sampling
• Write to every channel in one loop when using an FPGA I/O node
• Update to CompactRIO Device Drivers October 2019 (19.5)

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Host Memory Buffer read on FPGA can return FIFO data.

When using a Host Memory Buffer and a Host to Target DMA FIFO simultaneously, the Host Memory Buffer's Retrieve method on FPGA can incorrectly return data sent by the FIFO. This does not affect the FIFO's data in any way.

Workaround: Manually implement arbitration between Host-to-Target-FIFOs and the Host Memory Buffer's Request / Retrieve methods.  

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Cannot calibrate PXIe-7846R.

When calibrating the PXIe-7846R, either programmatically or when using the NI 78xxR Calibration Utility, the calibration may fail with the message "The device type of the chassis or FPGA target in the LabVIEW project does not match the actual type of device".

Workaround: Use LabVIEW 2016 and R Series Multifunction RIO 16.0 (August 2016). NI anticipates fixing this in an upcoming release.  

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SD Card LED on cRIO-903x and cDAQ-913x does not light up when SD card is inserted.

When SD card is inserted into cRIO-903x or cDAQ-913x "SD In Use" LED does not light up. The issue is purely visual and does not affect SD card operation. This issue does not affects devices with BIOS version 1.3.1f0 or higher.

Workaround: N/A

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Project & System Comparison utility fails to upload UDVs when a UDV is added with a channel index somewhere in the middle of existing indices.

When a user deletes existing user-defined variables in LabVIEW project and remakes new UDVs, they will be assigned deleted indices. The newly created UDVs should be assigned new indices. This then causes a discrepancy when using Compare Project & System between newly created UDVs and previously deployed but now deleted UDVs.

Workaround:

Deploy LabVIEW Project again 

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When using Host Memory Buffer and FPGA Interactive mode, the Real-Time process can encounter an exception and restart.

Applications using Host Memory Buffer (HMB) can encounter an exception and restart when running a Real-Time VI that accesses the Host Memory Buffer and a FPGA VI running in Interactive mode. This issue can present itself as a dialog box stating "Connection to the target...has been lost" followed by a notification on re-deploy that "(Hex 0x661) The LabVIEW Real-Time process encountered an unexpected error and restarted automatically." The issue can also present itself as a common error -63040 "A connection could not be established..." while trying to open an FPGA VI in Interactive mode.  

Workaround:

Restart the controller and connect to it in your LabVIEW Project. Start the Real-Time VI first, then start Interactive mode with the FPGA VI. Restart the RIO controller after each FPGA Interactive mode session (otherwise, you may encounter error -63040 while opening FPGA Interactive mode).

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Wifi cRIO-9032 and cRIO-9037 will not discover a 5GHz Wifi network operating on channel 60 in China.

Workaround:

If possible, select a different operating channel on your wifi source.

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Self-calibration VI for PXIe-7867 and PXIe-7868 is less accurate for analog output channels.

Workaround:

If possible, do not run self-calibration or install R Series MultifunctionRIO July 2017.

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