Each issue appears as a row in the table and includes the following fields:
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 504246 Return | Kintex-7 FPGA target may not download or change successfully in an NI PXI-1082 chassis. In rare instances, a Kintex-7 FPGA target may not download or change successfully in an NI PXI-1082 chassis. Workaround: Reboot the NI PXI-1082 chassis.
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| 631455 Return | Timing failures occur on deep DMA FIFOs on PXIe-6591R and PXIe-6592R devices. Large DMA FIFOs (greater than 32k elements) generate intermittent non-diagram timing errors when used with PXIe-6591R and PXIe-6592R devices. Workaround: Reduce the FIFO depth to fewer than 32k elements. You can also pipeline any signals connected to a DMA FIFO to help reduce timing failures.
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| 647327 Return | The PXIe-6592R 1GbE sample project's folders and files incorrectly reference the 10GbE example. The PXIe-6592R 1GbE sample project's HTML file incorrectly lists 10GbE in the file name. Some VIs reside in a folder labeled 10GbE. Additionally, the 10GigE.html file incorrectly states a transfer increment of 8 bytes; the 1GbE example can transfer data in increments of 1 byte. Workaround: Use the PXIe-6592R sample project for 1GbE applications only. The PXIe-6592R sample project does not support 10GbE applications.
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| 646292 Return | PXIe-7902 MGT Reference Clocks are incorrectly mapped in public documentation. The PXIe-7902 CLIP interfaces with an I/O socket that enumerates the following MGT Reference Clocks: MGT_RefCLK 2, MGT_RefCLK 3, and MGT_RefCLK 4. However, the project configuration and NI High-Speed Serial Instruments User Manual incorrectly list the available MGT Reference Clocks as MGT_RefClk0, MGT_RefClk1, and MGT_RefClk2. Workaround: Use MGT_RefCLK 2, MGT_RefCLK 3, and MGT_RefCLK 4 in the CLIP. These clocks map to MGT_RefCLK 0, MGT_RefCLK 1, and MGT_RefCLK 2, respectively, when configuring the clocks in the project explorer.
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| 503037 Return | PXIe-659xR Board Driver sessions may incorrectly read local devices when attempting to access remote devices. Board Driver methods (read temperature, power, and frequency counters) do not handle remote devices well. If you have a local device with the same RIO interface number as the remote device you are trying to access, you will read the power of the local device instead of the remote device. Workaround: Do not have any RIO devices on host computer.
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| 576099 Return | Error may be cleared in FPGA Close VI on Phar Lap RT. When using Phar Lap RT, the FPGA Close VI may clear an error that was generated earlier in the VI. This is most likely to occur while running Eye Scan, or using associated Eye Scan VIs. Workaround: Branch the error cluster wire around the FPGA Close VI and merge with the FPGA Close VI output error cluster wire.
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| 652132 Return | The Temperature Board IO node reports a code that is not in °C. The PXIe-7902 Aurora Getting Started example and the NI High-Speed Serial Instruments Help incorrectly state that the PXIe-7902 Board I/O item Device Temperature is reported in units of 0.01 °C. Workaround: Use the transfer function to correctly convert the ADC code reported by the Device Temperature into °C: (DeviceTemp * 503.975) / 4096 - 273.15
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The following list contains changes from earlier versions of NI LabVIEW Instrument Design Libraries for NI LabVIEW 2016 Instrument Design Libraries for High-Speed Serial Instruments. If you have a Bug ID, you can search this list to validate that the issue has been fixed. This is not an exhaustive list of issues fixed in the current version of NI LabVIEW Instrument Design Libraries for High-Speed Serial Instruments.
| Bug ID | Fixed Issue |
|---|---|
| NI LabVIEW 2016 Instrument Design Libraries for High-Speed Serial Instruments | |
| 520391 | Fixed an issue in the NI 6591R Simple Streaming Project that caused the Create AXI4-Lite Resources VI to create an invalid address space size for the project. |
| 530878 | Fixed an issue that inhibited exporting an external clock faster than 100 MHz. The new limit is 156.25 MHz. |
| 521583 | Fixed an issue that caused the Eye Scan to run with an incorrect sample multiplier. |
| 516064 | Fixed an issue that prevented creation of CLIP constraints using FPGA base clocks. |
| 511487 | Added the following missing error code: "-309809: You must specify at least one channel instance when calling Open Session.vi." |
Contact NI regarding this document or issues in the document. If you contact NI in regards to a specific issue, reference the ID number given in the document. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting NI). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Visit the NI Website to contact us. Also contact us if you find a workaround for an issue that is not listed in the document.