This document contains the LabVIEW 2016 FPGA Module known issues that were discovered before and since the release of LabVIEW 2016 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
The LabVIEW 2016 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.
The following items are known issues in LabVIEW 2016 FPGA Module sorted by Date.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 589137 Return | Incorrect synthesis of HDL case statement when importing external IP During synthesis, Vivado 2015.4 may incorrectly optimize out statements such as "if not (variableX = variableY) " in any external HDL code. This could lead to an unexpected implementation on the FPGA hardware. Refer to KB 7C7AGP08. Workaround: Change the statement to read "if variableX /= variableY then". Always test final hardware implementations.
| |||||
| 589796 Return | Duplicating example projects with an FPGA VI containing Read I/O Method or Get I/O Read Status Method causes an XNode error Copying an FPGA project, such as in the examples, by saving as a duplicate copy may throw an "Xnode is not executable" error if an FPGA VI within that project contains a Read I/O Method or Get I/O Read Status Method. Clicking on one of the modules within either of those methods after will show "No FPGA I/O Selectable". Workaround: Replace the broken methods with fresh methods from the Functions palette after the duplication.
| |||||
| 595635 Return | IP Builder does not correctly configure directives used on auto-indexed array indicators If the interface of an auto-indexed array is set to a directive of "All Elements", and the associated array buffer is also assigned a directive, then the compiler may resolve directive conflicts incorrectly. This results in an incorrect implementation of the design. Workaround: Avoid setting an interface directive of "All Elements" in combination with a directive for the array buffer of an auto-indexed indicator. Test all designs thoroughly after compilation.
| |||||
| 596659 Return | An XNode error may be thrown when an FPGA VI with a FIFO is changed while another FPGA VI is running interactively on the target If an FPGA VI is running interactively and a change is made to a different FPGA VI with that uses a FIFO, the FIFO methods will become broken with an unexpected Xnode error within the changed VI. Workaround: Make sure there are no interactive FPGA VIs running on the target before making changes to another FPGA VI that uses a FIFO. If an error occurs, stop the running VI, replace the FIFO invoke nodes and then make the desired changes.
| |||||
| 725737 Return | Digital Output timing outside of Single-Cycle Timed Loops has extra delay In LabVIEW 2014 SP1 FPGA and earlier, using Digital Outputs outside of a Single-Cycle Timed Loop would result in the output taking only a single cycle of the FPGA Base Clock to execute. Currently this takes several additional clock cycles. Workaround: Move Digital Outputs which have tight timing requirements into Single-Cycle Timed Loops.
|
The following items are known issues in LabVIEW 2016 FPGA Module sorted by Category.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| IP Builder | ||||||
| 595635 Return | IP Builder does not correctly configure directives used on auto-indexed array indicators If the interface of an auto-indexed array is set to a directive of "All Elements", and the associated array buffer is also assigned a directive, then the compiler may resolve directive conflicts incorrectly. This results in an incorrect implementation of the design. Workaround: Avoid setting an interface directive of "All Elements" in combination with a directive for the array buffer of an auto-indexed indicator. Test all designs thoroughly after compilation.
| |||||
| Miscellaneous | ||||||
| 589137 Return | Incorrect synthesis of HDL case statement when importing external IP During synthesis, Vivado 2015.4 may incorrectly optimize out statements such as "if not (variableX = variableY) " in any external HDL code. This could lead to an unexpected implementation on the FPGA hardware. Refer to KB 7C7AGP08. Workaround: Change the statement to read "if variableX /= variableY then". Always test final hardware implementations.
| |||||
| 589796 Return | Duplicating example projects with an FPGA VI containing Read I/O Method or Get I/O Read Status Method causes an XNode error Copying an FPGA project, such as in the examples, by saving as a duplicate copy may throw an "Xnode is not executable" error if an FPGA VI within that project contains a Read I/O Method or Get I/O Read Status Method. Clicking on one of the modules within either of those methods after will show "No FPGA I/O Selectable". Workaround: Replace the broken methods with fresh methods from the Functions palette after the duplication.
| |||||
| 596659 Return | An XNode error may be thrown when an FPGA VI with a FIFO is changed while another FPGA VI is running interactively on the target If an FPGA VI is running interactively and a change is made to a different FPGA VI with that uses a FIFO, the FIFO methods will become broken with an unexpected Xnode error within the changed VI. Workaround: Make sure there are no interactive FPGA VIs running on the target before making changes to another FPGA VI that uses a FIFO. If an error occurs, stop the running VI, replace the FIFO invoke nodes and then make the desired changes.
| |||||
| 725737 Return | Digital Output timing outside of Single-Cycle Timed Loops has extra delay In LabVIEW 2014 SP1 FPGA and earlier, using Digital Outputs outside of a Single-Cycle Timed Loop would result in the output taking only a single cycle of the FPGA Base Clock to execute. Currently this takes several additional clock cycles. Workaround: Move Digital Outputs which have tight timing requirements into Single-Cycle Timed Loops.
| |||||