ID | Known Issue |
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364860
| A deadlock can occur when creating two peer-to-peer streams between two devices in opposite directions concurrently
Workaround: To avoid the deadlock, serialize the calls to the niP2P Create Peer to Peer Stream VIs.
Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
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365340
| Running a VST sample project FPGA VI on a development computer with simulated I/O context causes LabVIEW to hang
Running a VST Sample Project FPGA VI on the development computer with simulated I/O context causes LabVIEW to hang because of the way LabVIEW FPGA allocates and uses the DRAM memory primitive when executing in the development computer context.
Workaround: There is no workaround to achieve full functionality, that is, to achieve the same waveform and record memory size available when running on hardware. However, you can use the following instructions to work around the LabVIEW memory issue:
- In the FPGA Target in your LabVIEW project, navigate to Memory/FIFOs»Acquisition»acq.data memory 0.
- Right-click acq.data memory 0 and select Properties.
- Under the General category, change the Requested number of elements to a smaller number, for example, 65,536.
- Repeat steps 2 and 3 for Memory/FIFOs»Generation»wfm seq.data memory 0.
- Change the memory size (128-bit elements) value in Acquisition.lvclass»Private»Constants.vi.
- Change the waveform memory size (num of 128-bit elements) value in Generation.lvclass»Private»Constants.vi.
Note: There is no guarantee that the rest of the sample project will work after you work around the LabVIEW memory issue.
Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
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363009
| The NI PXIe-5644R, NI PXIe-5645R, NI PXIe-5646R device may occasionally appear outside the chassis in MAX when the device is installed for the first time
The NI PXIe-5644R, NI PXIe-5645R, or NI PXIe-5646R device may occasionally appear outside the chassis in Measurement & Automation Explorer (MAX) when the hardware/software is installed for the first time. The device should still function properly.
Workaround: Restart the machine to get the device to appear in MAX properly.
Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
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364518
| Error –52018. A hardware failure has occurred. The operation could not be completed as specified
This error may occur when an instrument design VI accesses elements of an FPGA VI that are inside a Single Cycle Timed Loop (SCTL) that does not have a running clock. In this case, the problem is not a hardware failure and can be fixed by enabling the clock of the SCTL.
Workaround: Ensure that the SCTL clocks are running before calling the VI that returns the error.
Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
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453026
| When closing a newly created Simple VSA/VSG sample project, selecting Save in the Save Changes (Close Project) dialog box does not work
When closing a newly created Simple VSA/VSG sample project, selecting Save in the Save Changes (Close Project) dialog box does not work and the Save Changes (Close Project) dialog box does not close.
Workaround: There are two possible workarounds for this issue:
- Close a newly created Simple VSA/VSG sample project and select Don't Save in the Save Changes dialog box when prompted. This workaround will close the Save Changes dialog box, but will not save your sample project.
- Complete the following steps:
- Right-click FPGA Interface Type Definitions.lvlib in the sample project tree, and select Properties.
- In the General Settings category, select Separate compiled code from source file.
- Select OK to close the Properties dialog box.
- Close the project and choose Save when prompted.
Reported Version: Design Library 13.5 | | Resolved Version: N/A | | Added: 02/25/2014 |
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369338
| A dialog box prompts you to save a file when you create a VST sample project in localized LabVIEW
The first time you create a VST sample project (Simple VSA/VSG or Simple VST Streaming) in localized LabVIEW after installing instrument design libraries 2012.1, a dialog box prompts you to save niLvFpga_Open_PXIe-5644R.vi or similar.
Workaround: Click Save in the dialog box to continue creating the sample project.
Reported Version: Design Library 2012.1 | | Resolved Version: N/A | | Added: 04/05/2013 |
|
392126
| The niVST Calibration.lvlib:Self-Calibrate.vi leaks memory when loading and unloading
When using Self-Calibrate VI from the NI VST Calibration palette to self-calibrate the NI PXIe-5644R or NI PXIe-5645R, a memory leak may occur when loading and unloading the VI repeatedly.
Workaround: Keep the Self-Calibrate VI in memory. For example, in your top-level VI, create a "dummy" subVI that includes one instance of the Self-Calibrate VI to keep the Self-Calibrate VI loaded in memory. For applications that optimize memory usage where it is not acceptable to keep the Self-Calibrate VI in memory, you can minimize the memory leak by keeping a Timed Loop in memory. A memory leak will still exist, but it will be considerably smaller.
Reported Version: Design Library 2012.1 | | Resolved Version: N/A | | Added: 04/05/2013 |
|
414557
| Error –2147220623 occurs when a Simple VSA/VSG sample project created in design library 1.0 is run in design library 13.5
Running a Simple VSA/VSG sample project created with NI LabVIEW 2012 Support for NI PXIe-5644R 1.0.0 with current VST support returns error -2147220623.
Workaround: Complete the following steps to workaround this issue:
- In the Simple VSA/VSG sample project, navigate to Instrument Driver»Instrument Support - Shared.lvlib»Get RIO Product ID.vi.
- Open the Get RIO Product ID VI.
- Call the Create Filter VI after the Initialize Session VI, but before the Find VI. The Create Filter VI is located on the Functions palette at Measurement I/O»System Configuration»Utilities.
- Wire the session out and error out outputs of the Initialize Session VI to the session in and error in inputs of the Create Filter VI.
- If IsDev is not selected on the System Filter property node, click the first entry in the property node and select the Is Device property.
- Wire a Boolean constant to the IsDev input, and set it to True.
- Wire the System Session and error out outputs of the System Filter property node to the filter in and error in inputs of the Find VI.
Reported Version: Design Library 13.5 | | Resolved Version: N/A | | Added: 02/25/2014 |
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364736
| Waveform Sequencer does not generate any samples if the Set Priming Depth VI is set to a value of 4 samples or less
The Retrieve Waveform Sample FPGA VI of the Waveform Sequencer library does not generate any samples if you set the generation priming depth to a value less than or equal to 4 in the Set Priming Depth VI of the Waveform Sequencer host library.
Workaround: Configure the Set Priming Depth VI to a value of at least 5 samples; otherwise do not call the Set Priming Depth VI. If you do not call the Set Priming Depth VI, the application uses the default priming depth.
Reported Version: Design Library 1.0 | | Resolved Version: N/A | | Added: 08/28/2012 |
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452057
| The default value for Maximum outstanding requests for data on VST DRAM memory items is insufficient for maximum DRAM throughput
When creating a new DRAM memory item, the default value for Maximum outstanding requests for data is 32. This value must be changed to 64 to achieve maximum DRAM throughput on VST devices.
Workaround: Right-click a DRAM memory item under an FPGA Target in your LabVIEW project, and select Properties. In the General category, change the value for Maximum outstanding requests for data to 64.
Reported Version: Design Library 13.5 | | Resolved Version: N/A | | Added: 02/25/2014 |
|
425439
| When NI-RFSA and NI-RFSG both export a signal to the same external trigger line on a VST, LabVIEW does not return an error
It is possible to export two different signals to the same external trigger line on a VST, for example, NI-RFSG exports a Marker Event to PFI0, and NI-RFSA exports a Start Trigger to PFI0. However, LabVIEW does not return an error when this occurs, which causes only the last item that is configured within either driver to export its signal.
Workaround: Avoid exporting signals from both drivers to the same external trigger line.
Reported Version: RFSA/RFSG Support 13.0 | | Resolved Version: N/A | | Added: 02/25/2014 |
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411948
| Error –373104 occurs when a hyphen character is used in a configuration list name
When creating a configuration list in NI-RFSA or NI-RFSG on a VST target, the use of hyphens in the configuration list name results in error -373104, the specified configuration list name is invalid.
Workaround: Avoid using hyphen characters in configuration list names.
Reported Version: RFSA/RFSG Support 1.1 | | Resolved Version: N/A | | Added: 02/25/2014 |
|
464021
| The 802.11ac 80 MHz bandwidth and 160 MHz bandwidth with channel tracking enabled specifications are marked as warranted in the NI PXIe-5646R Specifications
The 802.11ac 80 MHz bandwidth and 160 MHz bandwidth with channel tracking enabled specifications are typical specifications. These specifications should be marked as typical specifications instead of warranted in the NI PXIe-5646R Specifications.
Workaround: N/A
Reported Version: 376125A-01, 326125A-01 | | Resolved Version: N/A | | Added: 04/10/2014 |
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