Archived: NI LabVIEW 2014 Instrument Design Libraries for CPRI 14.0 and 14.0.2 Known Issues

LabVIEW crashes when opening CPRI sample project after installing other NI instrument design libraries.
This error may occur when you install the instrument design libraries of other NI Modular Instruments such as the NI FlexRIO 15.5 driver. If you open the sample project, LabVIEW might crash with the following message: DAbort 0xEB526415.

Workaround: Install NI LabVIEW 2014 Instrument Design Libraries for CPRI 14.0.2 or later.

HDLC receive data in FPGA is not valid.
The CPRI CLIP allows low-level access to the HDLC interface of the CPRI logic in LabVIEW FPGA. The LabVIEW sample project contains stub functions on the block diagram (HDLC Rx.vi and HDLC Tx.vi) to illustrate this interface. However, the interface I/O signals hdlc0_rx_data and hdlc1_rx_data are always zero, even if HDLC data has been transmitted from the link partner.

Workaround: Install NI LabVIEW Instrument Design Libraries for CPRI 14.0.2 or later. This version contains a fixed FPGA netlist for the CPRI CLIP. After installation, recompile your LabVIEW FPGA design bitfile.

The CPRI Physical Layer (FPGA) resets the transmitter periodically if no HFNSYNC is detected from the receiver.
In remote radio heads, some CPRI slave implementations start to transmit a valid CPRI signal only after they complete clock synchronization with the CPRI master. The clock synchronization might take up to about 300 ms. The current implementation prevents a successful clock synchronization because the NI PXIe-6592R, as a CPRI master, will reset it's transmitter every 4.6 ms when no valid data from the CPRI slave is received.

Workaround: There are two possible workarounds for this issue:

• Install NI LabVIEW Instrument Design Libraries for CPRI 14.0.1 or later. Then you can create the CPRI Acquisition and Generation (NI 6592R) sample project, which will contain an updated version of the CPRI Control.lvclass:Initiate Link VI.
• Modify your existing sample project to disable Physical Layer (FPGA) link setup time-out in CPRI master mode by using the niCPRI Target Control Base v1 Host.lvclass:Set PHY Watchdog VI.

When creating a new project in LabVIEW 64-bit from the CPRI Acquistion and Generation (NI 6592R) sample project template, LabVIEW asks to save niLvFpga_Open_PXIe-6592R.vi.
When creating a new project in LabVIEW 64-bit from the CPRI Acquistion and Generation (NI 6592R) sample project template, LabVIEW asks to save niLvFpga_Open_PXIe-6592R.vi located at C:\Program Files\National Instruments\LabVIEW 2014\vi.lib\FPGAPlugInAG\PXIe-6592R.

Workaround: When LabVIEW asks, save niLvFpga_Open_PXIe-6592R.vi.

The CPRI Acquisition and Generation (6592R) sample project returns errors when either the acquisition or generation Host VIs are not present in FPGA bitfile.
If you remove either the acquisition or generation Host VIs from the FPGA bitfile, the CPRI Acquisition and Generation (6592R) sample project Host VIs return errors. This occurs even if no acquisition or generation Host VIs are executed.

Workaround: If you want to use an FPGA bitfile without acquisition or generation Host VIs, you need to remove all references to the multirecord acquisition and waveform generation libraries in the sample project.

The CPRI Acquisition and Generation (NI 6592R) sample project does not support ACQUISITION_CPRI_PORT0 := FALSE or ACQUISITION_CPRI_PORT1 := FALSE conditional disable symbol settings.

Workaround: Remove the VIs related to I/Q data acquisition manually from the top-level CPRI Acquisition and Generation (FPGA) VI.

The Ethernet throughput over the CPRI link does not exploit the full capacity of the fast C&M plane.
The Ethernet throughput over the CPRI link does not exploit the full capacity of the fast control and measurement (C&M) plane. The current implementation of the Ethernet over CPRI functionality transfers Ethernet frames between the 1 Gigabit Ethernet Ports 2 or 3 and the CPRI Ports 0 or 1, respectively. However, the 1 Gigabit Ethernet Port 2 and 3 can exceed the throughput capacity of the CPRI link, and the corresponding Ethernet frames are discarded. The use of the transmission control protocol (TCP) ensures that discarded IP packets are re-transmitted. The CPRI fast C&M plane capacity is defined in Table 12: Achievable Ethernet bit rates in the CPRI Specification version 5.0, and depends on the CPRI line bit rate option and the Ethernet pointer. The actual Ethernet throughput is usually much lower than the specified throughput capacity when measured.

Workaround: Complete the following workaround to increase the actual Ethernet throughput by reducing the maximum transfer unit (MTU) size:

1. To view the current MTU setting on Windows 7, open a command line terminal and enter the following:
   netsh interface ipv4 show interfaces
2. Change the MTU setting by entering the following:
   netsh interface ipv4 set subinterface x mtu=200 store=persistent
   where x is your network interface IDx value.

Setting the MTU to 200 increases the Ethernet throughput by about 50% of the throughput capacity. The setting must be applied on all network interfaces that use the Ethernet over CPRI interface.

Note: Decreasing the MTU does have a negative impact on your general network performance.

The Ethernet over CPRI interface (Fast C&M plane) is not functional for CPRI Line Bit Rate 1 (614.4 Mbps).
The Ethernet over CPRI interface (Fast C&M plane) is not functional for CPRI Line Bit Rate 1 (614.4 Mbps). If you configure the CPRI link to use CPRI Line Bit Rate 1 (614.4 Mbps), the Ethernet packet data is not transmitted or received over the CPRI link.

Workaround: Choose a CPRI Line Bit Rate other than 1 to use the Ethernet over CPRI interface (Fast C&M plane).

When closing a newly created CPRI Acquisition and Generation (NI 6592R) sample project, selecting Save in the Save Changes? (Close Project) dialog box does not work.
When closing a newly created CPRI Acquisition and Generation (NI 6592R) sample project, selecting Save in the Save Changes? (Close Project) dialog box does not work. The Save Changes? (Close Project) dialog box does not close until either Don't Save or Cancel is selected.

Workaround: There are two possible workarounds for this issue:

• Select Don't Save in the Save Changes? (Close Project) dialog box.
• Complete the following steps:
  1. In the Project Explorer window, navigate to My Computer»FPGA[CPRI 2x, ETH 2x] (RIO0, PXIe-6592R), right-click on CPRI FPGA Interface Type Definitions.lvlib and select Properties.
  2. In the Project Library Properties dialog box, navigate to the General Settings category, and select the Separate compiled code from source file checkbox.
  3. Select OK to close the Project Library Properties dialog box.
  4. Close the project and select Save in the Save Changes? (Close Project) dialog box.

The Initiate Generation VI does not generate samples if the waveform data is 4 basic frames or less.
If the waveform data is 4 basic frames or less, the Initiate Generation VI does not transmit I/Q data over the CPRI user plane and the Generation Status output in the Get Generation State VI does not return Generation Running or Generation Done.

Workaround: Use a longer waveform data set. The minimum waveform length is five basic frames. You can replicate data or fill in zeros as needed.