NI does not actively maintain this document.
This content provides support for older products and technology, so you may notice outdated links or obsolete information about operating systems or other relevant products.
This document contains the LabVIEW 2013 FPGA IP Builder known issues that were discovered before and since the release of LabVIEW 2013 FPGA IP Builder. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
The LabVIEW 2013 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.
The following items are known issues in LabVIEW FPGA IP Builder 2013 sorted by Category.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| LV FPGA IP Builder | ||||||
| 336983 Return | LabVIEW does not return estimation errors despite conflicts between directive settings LabVIEW may not return estimation errors, but may return build errors when you configure directive settings that conflict with each other. For example, if the top-level VI of the algorithm contains an array control and you wire this array directly into a subVI. In the subVI, you access the array elements sequentially. LabVIEW does not return estimation errors if you apply the following directive settings that conflict with each other: * Use the "Element-by-element, unbuffered" option for the array control on the top-level VI interface; * Use the "Complete" partition type for the same array in the subVI. Workaround: Do not specify conflicting directives. To resolve the build error in this specific example, either change "Element-by-element, unbuffered" to "All elements" or disable partitioning for this array.
| |||||
| 315926 Return | FPGA IP Builder does not support Boolean controls with latch mechanical actions FPGA IP Builder does not implement the latch mechanical actions on Boolean controls. All Boolean controls in the FPGA IP Builder context are treated as controls with switching mechanical actions. Workaround: Modify the Boolean controls to use the switching mechanical action.
| |||||
| 356405 Return | Unexpected error might occur if the algorithm VI contains FPGA Module Express VIs If the algorithm VI contains any of the following FPGA Module Express VIs, you still can create a directives item for this VI. You also can create build specifications for this directives item. However, an unexpected error might occur when you double-click this directives item or generate FPGA IP from the build specifications: * Sine Wave Generator * Square Wave Generator * White Noise Generator * Quantizer * Basic Discrete Delay * Look-Up Table 1D Workaround: When you create algorithm VIs, avoid using the FPGA Module Express VIs listed above.
| |||||
| 395702 Return | FPGA IP Builder-generated VIs do not strictly distinguish between SGL positive zero and SGL negative zero FPGA IP Builder does not guarantee the sign bit accuracy for SGL positive zero values and SGL negative zero values of FPGA IP Builder-generated VIs. You may get an SGL negative zero value result in FPGA IP Builder-generated VIs, even though you get an SGL positive zero value result in LabVIEW. Workaround: N/A
| |||||
| 404538 Return | You encounter a warning when applying an "Element-by-element, unbuffered" interface on an array control/indicator If you apply an "Element-by-element, unbuffered" interface on an array control/indicator, you may get a warning in Design Feedback report, such as "Array "x" is an element-by-element, unbuffered array which contains one of the following issues: (1) the VI accesses some elements more than once; (2) the VI does not use some elements; or (3) the VI does not access the elements in sequential order." This warning might be a false alarm for some cases. Workaround: If you require an "Element-by-element, unbuffered" interface, double-check your algorithm VI to make sure that you do not violate any of the three criteria mentioned in the Design Feedback report warning. You should also verify the generated IP through emulation before applying it in a true application. You can also consider applying an "Element-by-element, buffered" interface. An "Element-by-element, buffered" interface will increase the latency, lower the throughput, and use more memory resources.
| |||||
| 411025 Return | LabVIEW can report incorrect Initiation Interval and Latency if your design is not pipelined If you have multiple subVIs or primitive nodes like To SGL, Square Root and Divide, in a Loop or a VI, and don't specify Initial Interval to the owning loop or owning VI, LabVIEW can report incorrect latencies during estimation and build. In such cases, the corresponding Initiation Interval is equal to (Latency+1) so that the reported Initiation Interval could also be wrong. Workaround: To prevent getting data at incorrect cycles, please always use handshaking signals to obtain the actual Initiation Intervals and Latencies at run-time. To work around such issues, you may apply the Initiation Internal directive to the owning loop or VI.
| |||||
| 411104 Return | FPGA IP Builder-generated VIs do not produce full-precision results for SGL reciprocal operations on Spartan-6, Virtex-6, Kintex-7, and Zynq targets FPGA IP Builder does not guarantee the least-significant bit accuracy for SGL reciprocal operation results of FPGA IP Builder-generated VIs on Spartan-6, Virtex-6, Kintex-7, or Zynq targets. Although FPGA IP Builder does not support SGL functionality for the Reciprocal function directly, you may use the Divide function or the Compound Arithmetic function to perform SGL reciprocal operations. However, SGL reciprocal operations may produce different results in FPGA IP Builder-generated VIs than in LabVIEW. Workaround: If you want to calculate full-precision reciprocal results of SGL data y on Spartan-6, Virtex-6, Kintex-7, or Zynq targets, follow these steps: first, create an SGL control x in the top-level algorithm VI; second, connect the control x to the connector pane of the top-level algorithm VI; third, connect the control x to the x input of the Divide function and data y to the y input of the Divide function; next, compile the algorithm VI; finally, set x to 1.0 in the top-level VI when you invoke the generated VI.
| |||||
| 413363 Return | LabVIEW may report an unexpected error if you use ModelSim as a third-party simulator for LabVIEW FPGA VIs which invoke FPGA IP Builder-generated VIs If a LabVIEW FPGA VI invokes an FPGA IP Builder-generated VI and you use ModelSim as the third-party simulator for the FPGA Target, LabVIEW may report an unexpected error when you build the Simulation Export. Workaround: There are two ways to resolve this issue: You can use ISim as the third-party simulator to perform the simulation. To set ISim as the third-party simulator, open Tools->Options...->FPGA Module->Simulation and set ISim as the simulator. Then, rebuild the Simulation Export and follow the general procedures to perform third-party simulation. You also can use ModelSim as the third-party simulator to perform the simulation if you first modify the VHDL file that ends with _topH.vhd under the FPGA IP Builder supporting files directory. You can modify the VHDL file according to the following steps: 1. Add the signal declaration sentence "signal ap_start: std_logic;" to the architecture declaration section. 2. Add the signal assignment sentence "ap_start <= not first_call;" to the architecture body. 3. Map the port ap_start of APWrapper_Block to the new signal ap_start, like this: "ap_start => ap_start,". 4. Save the modified VHDL file and close it. 5. Double-click the IP Integration Node in the IP Builder-generated VI and regenerate the node manually with the same configuration as before you made the changes. After you finish generating the node, you need to save the IP Builder-generated VI and close it. Finally, rebuild the Simulation Export and follow the general procedures to perform third-party simulation.
| |||||
The following items are known issues in LabVIEW FPGA IP Builder 2013 sorted by Date.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 336983 Return | LabVIEW does not return estimation errors despite conflicts between directive settings LabVIEW may not return estimation errors, but may return build errors when you configure directive settings that conflict with each other. For example, if the top-level VI of the algorithm contains an array control and you wire this array directly into a subVI. In the subVI, you access the array elements sequentially. LabVIEW does not return estimation errors if you apply the following directive settings that conflict with each other: * Use the "Element-by-element, unbuffered" option for the array control on the top-level VI interface; * Use the "Complete" partition type for the same array in the subVI. Workaround: Do not specify conflicting directives. To resolve the build error in this specific example, either change "Element-by-element, unbuffered" to "All elements" or disable partitioning for this array.
| |||||
| 315926 Return | FPGA IP Builder does not support Boolean controls with latch mechanical actions FPGA IP Builder does not implement the latch mechanical actions on Boolean controls. All Boolean controls in the FPGA IP Builder context are treated as controls with switching mechanical actions. Workaround: Modify the Boolean controls to use the switching mechanical action.
| |||||
| 356405 Return | Unexpected error might occur if the algorithm VI contains FPGA Module Express VIs If the algorithm VI contains any of the following FPGA Module Express VIs, you still can create a directives item for this VI. You also can create build specifications for this directives item. However, an unexpected error might occur when you double-click this directives item or generate FPGA IP from the build specifications: * Sine Wave Generator * Square Wave Generator * White Noise Generator * Quantizer * Basic Discrete Delay * Look-Up Table 1D Workaround: When you create algorithm VIs, avoid using the FPGA Module Express VIs listed above.
| |||||
| 395702 Return | FPGA IP Builder-generated VIs do not strictly distinguish between SGL positive zero and SGL negative zero FPGA IP Builder does not guarantee the sign bit accuracy for SGL positive zero values and SGL negative zero values of FPGA IP Builder-generated VIs. You may get an SGL negative zero value result in FPGA IP Builder-generated VIs, even though you get an SGL positive zero value result in LabVIEW. Workaround: N/A
| |||||
| 404538 Return | You encounter a warning when applying an "Element-by-element, unbuffered" interface on an array control/indicator If you apply an "Element-by-element, unbuffered" interface on an array control/indicator, you may get a warning in Design Feedback report, such as "Array "x" is an element-by-element, unbuffered array which contains one of the following issues: (1) the VI accesses some elements more than once; (2) the VI does not use some elements; or (3) the VI does not access the elements in sequential order." This warning might be a false alarm for some cases. Workaround: If you require an "Element-by-element, unbuffered" interface, double-check your algorithm VI to make sure that you do not violate any of the three criteria mentioned in the Design Feedback report warning. You should also verify the generated IP through emulation before applying it in a true application. You can also consider applying an "Element-by-element, buffered" interface. An "Element-by-element, buffered" interface will increase the latency, lower the throughput, and use more memory resources.
| |||||
| 411025 Return | LabVIEW can report incorrect Initiation Interval and Latency if your design is not pipelined If you have multiple subVIs or primitive nodes like To SGL, Square Root and Divide, in a Loop or a VI, and don't specify Initial Interval to the owning loop or owning VI, LabVIEW can report incorrect latencies during estimation and build. In such cases, the corresponding Initiation Interval is equal to (Latency+1) so that the reported Initiation Interval could also be wrong. Workaround: To prevent getting data at incorrect cycles, please always use handshaking signals to obtain the actual Initiation Intervals and Latencies at run-time. To work around such issues, you may apply the Initiation Internal directive to the owning loop or VI.
| |||||
| 411104 Return | FPGA IP Builder-generated VIs do not produce full-precision results for SGL reciprocal operations on Spartan-6, Virtex-6, Kintex-7, and Zynq targets FPGA IP Builder does not guarantee the least-significant bit accuracy for SGL reciprocal operation results of FPGA IP Builder-generated VIs on Spartan-6, Virtex-6, Kintex-7, or Zynq targets. Although FPGA IP Builder does not support SGL functionality for the Reciprocal function directly, you may use the Divide function or the Compound Arithmetic function to perform SGL reciprocal operations. However, SGL reciprocal operations may produce different results in FPGA IP Builder-generated VIs than in LabVIEW. Workaround: If you want to calculate full-precision reciprocal results of SGL data y on Spartan-6, Virtex-6, Kintex-7, or Zynq targets, follow these steps: first, create an SGL control x in the top-level algorithm VI; second, connect the control x to the connector pane of the top-level algorithm VI; third, connect the control x to the x input of the Divide function and data y to the y input of the Divide function; next, compile the algorithm VI; finally, set x to 1.0 in the top-level VI when you invoke the generated VI.
| |||||
| 413363 Return | LabVIEW may report an unexpected error if you use ModelSim as a third-party simulator for LabVIEW FPGA VIs which invoke FPGA IP Builder-generated VIs If a LabVIEW FPGA VI invokes an FPGA IP Builder-generated VI and you use ModelSim as the third-party simulator for the FPGA Target, LabVIEW may report an unexpected error when you build the Simulation Export. Workaround: There are two ways to resolve this issue: You can use ISim as the third-party simulator to perform the simulation. To set ISim as the third-party simulator, open Tools->Options...->FPGA Module->Simulation and set ISim as the simulator. Then, rebuild the Simulation Export and follow the general procedures to perform third-party simulation. You also can use ModelSim as the third-party simulator to perform the simulation if you first modify the VHDL file that ends with _topH.vhd under the FPGA IP Builder supporting files directory. You can modify the VHDL file according to the following steps: 1. Add the signal declaration sentence "signal ap_start: std_logic;" to the architecture declaration section. 2. Add the signal assignment sentence "ap_start <= not first_call;" to the architecture body. 3. Map the port ap_start of APWrapper_Block to the new signal ap_start, like this: "ap_start => ap_start,". 4. Save the modified VHDL file and close it. 5. Double-click the IP Integration Node in the IP Builder-generated VI and regenerate the node manually with the same configuration as before you made the changes. After you finish generating the node, you need to save the IP Builder-generated VI and close it. Finally, rebuild the Simulation Export and follow the general procedures to perform third-party simulation.
|
Document last updated on 8/1/2013