NI-RIO 4.0.0 and 4.1.0 Known Issues

Calling the Mount method for a NI 9802 module on the wrong slot number will sometimes result in a crash on VxWorks targets

When running the Mount method for a NI 9802 from the Real-Time host, entering the wrong slot number can result in a crash on VxWorks targets.

Workaround:  

Ensure a NI 9802 module is in the correct slot before running the Mount method.

Possible timing errors when compiling a VI with an NI 9215 IO node

Compiling an FPGA VI with 9215 IO nodes will potentially fail timing constraints.

Workaround:  

The failure should only occur intermittently and recompiling the FPGA VI usually executes successfully.

Setting Range property on 9219 with other properties in the same property node returns error -65720

Using a property node that includes 'Range' and any other property specific to the same channel of a 9219 will return Error -65720: This property is not valid for this module, or is not valid for the current configuration of this module. This error will be returned even though the configuration is valid.

Workaround:  

When writing the Range property, write to it in a property node separate from other properties.

Deploying an NI 9870 or 9871 when the module isn't physically present corrupts the CompactRIO RT controller

If a project is configured to contain an NI 9870 or 9871 module but the module isn't physically in the chassis, deploying the chassis will result in software corruption on VxWorks controllers. This and subsequent deployments will result in the following error: LabVIEW: (Hex 0x80DF0019) The deployment connection has timed out. To determine which operating system your controller is running, refer to Knowledgebase 4LRA4IQ0: What Operating System is my Real-Time Controller Running and Why?

Workaround:  

None.

NI sbRIO-9632/9642 boards can output incorrect analog output values on built-in AO channels when used in Scan Mode

When used in Scan Interface mode, the built-in analog output channels of NI sbRIO-9632/9642 devices may output a voltage very different from the commanded value. 

Workaround:  

Use the chassis in hybrid mode by compiling and deploying a user-defined FPGA VI. This issue was also corrected by a patch for NI-RIO in December 2011 and the patch was integrated into NI-RIO 4.1.0.

LabVIEW executables that include RSI module property nodes will not run

Using LabVIEW Application Builder to create an executable that uses property nodes for RIO Scan Interface modules will not run correctly due to missing dependencies.

Workaround:

None.

Existing User-Defined Variables stop working after adding new ones

If you make a change to the collection of User-Defined Variables (UDV) and then attempt to run your RT VI, you'll get an expected error telling you to recompile your FPGA VI.  Once you do this, your FPGA VI will load but all UDV will return an "invalid refnum" error.  

Workaround:  

To complete the system update and add the new UDV to the system, you will also need to explicitly deploy these variables.  Right-click on the controller, select Undeploy, then right-click the controller again and select deploy.

NI 9075/9076 have modified DMA specifications

These chassis have slight different DMA specifications than previous CompactRIO chassis.  These differences are listed in the NI-RIO help file at:
NI-RIO>>C Series References and Procedures>>Devices>>CompactRIO Chassis>>NI cRIO-9075

Keep in mind the following guidelines for writing to DMA FIFOs on the NI cRIO-9075:

--Always check the Empty Elements Remaining indicator from any previous DMA write operation before doing the next DMA FIFO write.

--The DMA engine transfers data in 64-byte chunks. If the host FIFO is full, reading data in amounts that are non-multiples of 64 bytes from either the FPGA FIFO or the host FIFO does not necessarily free an equivalent amount of space on the other FIFO.

--The DMA host FIFO size is limited to 2,096,960 bytes.

Workaround:  

This issue has been resolved in NI-RIO 4.1.0. If you need a DMA FIFO larger than 2 MB on the NI 9075/9076 you must upgrade to NI-RIO 4.1.0 or later.

NI 9802 Mount and Unmount methods cannot be called remotely from Windows

Normally, these commands would be run from the RT controller host (or remotely on the RT host through VI Server). For the EthernetRIO targets, NI 9146/9148 this is not an option.  This means that the NI 9802 RT API cannot be used with these targets.

Workaround:  

None.

Possible timing errors when compiling a VI with a 9476/9477 IO node on a Spartan 3 target at 80 MHz

An IO node with 32 channels and error terminals enabled will not successfully compile on a Spartan 3 (sbRIO-96xx, cRIO-907x) when the top level clock is set to 80 MHz

Workaround:

Setting the Design Strategy to Timing performance in the build specification property for Xilinx Options will allow this to compile.  Alternatively, splitting the IO node into two 16-channel IO nodes will be successful.

Getting INTERNAL_ERROR:Xst:cmain.c:3464:1.47.6.4 when compiling a 9205/9206 for a Spartan 3 target with an 80 MHz clock

This is a known issue with the Xilinx compiler that only occurs in rare situations.

Workaround:

Changing parts of the block diagram might fix the issue; alternatively, setting the Xilinx Options for Design Strategy to by optimized for Timing Performance should resolve the issue.  

Timing violations with certain modules when compiling for a Spartan 3 target at 80 MHz

When using a 9205, 9206, 9263, 9264, or 9269 module with an 80 MHz clock on a Spartan 3 target (NI 96xx or NI 907x) it’s possible to get a timing failure when compiling.

Workaround:

In the Xilinx options, select the Design Strategy to be optimized for Timing Performance.  

Configuring a module in scan mode that has been swapped for another without restarting causes error 1070

If a module being used in scan mode is swapped out and replaced, “Refresh Modules” command will pick up the difference; however, trying to programmatically configure the module results in “Error 1070”

The module is implicitly opening a reference that is not being refreshed

Workaround:

(1) To programmatically prevent the issue, explicitly close both references (IO and module) by calling “Close Variable Connection” from the Shared Variables Palette, before running Discover IO.vi  (2) If the VI is stopped and started again the references will be updated properly.

Chassis settings don't automatically deploy

Changes to the chassis properties are not automatically deployed.  This is problematic when switching between Scan and FPGA Interface mode because it means the project can easily get out of sync with the target if the user does not manually deploy the chassis.

Workaround:

Manually deploy settings whenever changes are made to chassis properties.

Mounting/Unmounting a NI 9802 in Real-Time interrupts Scan Engine

When you take scan mode measurements and then mount and unmount the SD card, on the subsequent reads the scan mode I/O variable throws error -65536 until the FPGA VI is run.

Workaround:

Instead of the blank FPGA VI required to normally make this work, use an empty while loop inside the FPGA VI and leave this VI running while running the RT VI.

Changing counter configuration via module refnum always resets counter

When changing properties such as terminal count and counter direction via the RSI module refnum the counter value always resets.

Workaround: 

None.

Performance issues when using more than 16 FPGA sessions

The NI-RIO driver maintains a growable lookup table of sessions that has segments. If the first segment overflows, new segments are created. RIO sessions using those new segments will pay a performance penalty. The RIO driver sets a warning on any session that has this "problem".

Workaround:

Users should be careful to close unused sessions and look for sessions leaks.  If greater than 16 sessions are needed, please contact NI technical support.  

DMA is not supported from the host to the FPGA on cRIO-900x

DMA is not supported from the host to the FPGA target on the cRIO-9002/9004.

LabVIEW returns an error if you try to output DMA from the cRIO-9002/9004.

Workaround:

None.

Existing User-Defined Variables stop working after adding new ones

If you make a change to the collection of User-Defined Variables (UDV) and then attempt to run your RT VI, you'll get an expected error telling you to recompile your FPGA VI.  Once you do this, your FPGA VI will load but all UDV will return an "invalid refnum" error.  

Workaround:  

To complete the system update and add the new UDV to the system, you will also need to explicitly deploy these variables.  Right-click on the controller, select Undeploy, then right-click the controller again and select deploy.

NI 9075/9076 cannot read TEDS data

If you try to use TEDS functionality with the NI 9075/9076, the FPGA VI will compile fine but the host VI will have a broken run arrow when a Read TEDS method node is placed on the block diagram. 

The error is:

An internal software error has occurred. Contact National Instruments technical support at ni.com/support. Error details:
-61499 : Could not find plugin VI path in resource tree.
Method: Read TEDS
Target Class: cRIO-9076

Workaround:  

This has been fixed for NI-RIO 4.0.0 with LabVIEW 2011.  If you are planning to use TEDS sensors with a NI 9075/9076 you must upgrade to NI-RIO 4.0.0 and LabVIEW 2011.

NI 9075/9076 do not support RIO Scan Interface or Hybrid modes

The new NI 9075/9076 integrated chassis and controller CompactRIO devices did not initially ship with RIO Scan Interface (RSI) capability.

However, the "Chassis Properties" dialog box used to select FPGA or RSI mode alludes to the fact that the controller may be used in Hybrid Mode.  

Workaround:  

RSI support was added to NI-RIO 4.0.0 with LabVIEW 2011.  If you need to use RSI or Hybrid mode with the NI 9075/9076 you must upgrade to NI-RIO 4.0.0 and LabVIEW 2011.

NI 9075/9076 have modified DMA specifications

These chassis have slight different DMA specifications than previous CompactRIO chassis.  These differences are listed in the NI-RIO help file at:
NI-RIO>>C Series References and Procedures>>Devices>>CompactRIO Chassis>>NI cRIO-9075

Keep in mind the following guidelines for writing to DMA FIFOs on the NI cRIO-9075:

--Always check the Empty Elements Remaining indicator from any previous DMA write operation before doing the next DMA FIFO write.

--The DMA engine transfers data in 64-byte chunks. If the host FIFO is full, reading data in amounts that are non-multiples of 64 bytes from either the FPGA FIFO or the host FIFO does not necessarily free an equivalent amount of space on the other FIFO.

--The DMA host FIFO size is limited to 2,096,960 bytes.

Workaround:  

None.

NI 9802 Mount and Unmount methods cannot be called remotely from Windows

Normally, these commands would be run from the RT controller host (or remotely on the RT host through VI Server). For the EthernetRIO targets, NI 9146/9148 this is not an option.  This means that the NI 9802 RT API cannot be used with these targets.

Workaround:  

None.

Scan Engine VIs fail on a machine with only LabVIEW runtime & NI-RIO

Scan Engine VIs (such as "Set Scan Engine Mode.vi") return an error when use in a built LabVIEW application on a machine which only has the LabVIEW runtime & NI-RIO driver installed (returns error -2132869114: A Module could not be loaded).  The same LabVIEW exe works fine on a machine which also has the LabVIEW development environment installed.

Workaround:  

The Scan Engine VIs need the DLLs located in:

C:\Program Files\National Instruments\Shared\DeploymentFramework

Copy this directory onto the machine with only LV runtime & NI-RIO, (in the same location) and the scan engine VIs will function properly. This DeploymentFramework folder is installed with the LabVIEW development environment, but not with LabVIEW runtime or NI-RIO driver.

Possible timing errors when compiling a VI with a 9476/9477 IO node on a Spartan 3 target at 80 MHz

An IO node with 32 channels and error terminals enabled will not successfully compile on a Spartan 3 (sbRIO-96xx, cRIO-907x) when the top level clock is set to 80 MHz.

Workaround:

Setting the Design Strategy to Timing performance in the build specification property for Xilinx Options will allow this to compile.  Alternatively, splitting the IO node into two 16-channel IO nodes will be successful.

Getting INTERNAL_ERROR:Xst:cmain.c:3464:1.47.6.4 when compiling a 9205/9206 for a Spartan 3 target with an 80 MHz clock

This is a known issue with the Xilinx compiler that only occurs in rare situations.

Workaround:

Changing parts of the block diagram might fix the issue; alternatively, setting the Xilinx Options for Design Strategy to by optimized for Timing Performance should resolve the issue.  

Timing violations with certain modules when compiling for a Spartan 3 target at 80 MHz

When using a 9205, 9206, 9263, 9264, or 9269 module with an 80 MHz clock on a Spartan 3 target (NI 96xx or NI 907x) it’s possible to get a timing failure when compiling.

Workaround:

In the Xilinx options, select the Design Strategy to be optimized for Timing Performance.  

Configuring a module in scan mode that has been swapped for another without restarting causes error 1070

If a module being used in scan mode is swapped out and replaced, “Refresh Modules” command will pick up the difference; however, trying to programmatically configure the module results in “Error 1070”.

The module is implicitly opening a reference that is not being refreshed.

Workaround:

(1) To programmatically prevent the issue, explicitly close both references (IO and module) by calling “Close Variable Connection” from the Shared Variables Palette, before running Discover IO.vi  (2) If the VI is stopped and started again the references will be updated properly.

Chassis settings don't automatically deploy

Changes to the chassis properties are not automatically deployed.  This is problematic when switching between Scan and FPGA Interface mode because it means the project can easily get out of sync with the target if the user does not manually deploy the chassis.

Workaround:

Manually deploy settings whenever changes are made to chassis properties.

Mounting/Unmounting a NI 9802 in Real-Time interrupts Scan Engine

When you take scan mode measurements and then mount and unmount the SD card, on the subsequent reads the scan mode I/O variable throws error -65536 until the FPGA VI is run.

Workaround:

Instead of the blank FPGA VI required to normally make this work, use an empty while loop inside the FPGA VI and leave this VI running while running the RT VI.

Changing counter configuration via module refnum always resets counter

When changing properties such as terminal count and counter direction via the RSI module refnum the counter value always resets.

Workaround: 

None.

Reading Empty Target to Host DMA FIFO with Timeout Set to Zero Gradually Starves CPU in built LabVIEW RT executables on cRIO targets

In built LabVIEW RT applications on cRIO, if a Target to Host DMA FIFO read executes with a timeout of zero and the FIFO is empty a processor leak occurs that increases the CPU usage on the controller.

Workaround:

Read zero elements to find elements remaining, instead of using a zero timeout.

Performance issues when using more than 16 FPGA sessions

The NI-RIO driver maintains a growable lookup table of sessions that has segments. If the first segment overflows, new segments are created. RIO sessions using those new segments will pay a performance penalty. The RIO driver sets a warning on any session that has this "problem".

Workaround:

Users should be careful to close unused sessions and look for sessions leaks.  If greater than 16 sessions are needed, please contact NI technical support.  

DMA is not supported from the host to the FPGA on cRIO-900x

DMA is not supported from the host to the FPGA target on the cRIO-9002/9004.

LabVIEW returns an error if you try to output DMA from the cRIO-9002/9004.

Workaround:

None.

Known Issue

Configuring a module in scan mode that has been swapped for another without restarting causes error 1070

If a module being used in scan mode is swapped out and replaced, “Refresh Modules” command will pick up the difference; however, trying to programmatically configure the module results in “Error 1070”.

The module is implicitly opening a reference that is not being refreshed.

Workaround:

(1) To programmatically prevent the issue, explicitly close both references (IO and module) by calling “Close Variable Connection” from the Shared Variables Palette, before running Discover IO.vi  (2) If the VI is stopped and started again the references will be updated properly.

FPGA Discovery fails silently on sbRIO if FPGA is in a bad state

Anytime the sbRIO is in the following states: safe mode, unconfigured IP address, or the NI-RIO driver is not installed on the controller, FPGA auto-discovery will fail silently.

Note1 -- If the sbRIO controller is in a good state, auto-discovery succeeds.
Note2 -- If there is some condition that prevents module discovery (not FPGA target discovery) from working during sbRIO auto-discovery, it is reported correctly.
Note3 -- cRIO autodiscovery reports errors properly at every stage

Workaround:

Manually add the FPGA target.

Chassis settings don't automatically deploy

Changes to the chassis properties are not automatically deployed.  This is problematic when switching between Scan and FPGA Interface mode because it means the project can easily get out of sync with the target if the user does not manually deploy the chassis.

Workaround:

Manually deploy settings whenever changes are made to chassis properties.

Mount SD Card (9802) Doesn't return error on Pharlap

The NI 9802 is not supported on Pharlap targets (900x). 

If an attempt to mount the NI 9802 in LabVIEW Real-Time is made it will not work; however, no error is returned.  The drive letter returned is “/” which is the only indication this didn’t work.

Workaround:

None.

cRIO-9074 set to Ethernet polling still uses interrupt based Ethernet

When Ethernet polling is enabled on this controller it still gets interrupts anyway, causing jitter.

Workaround:

None.

9401 output glitches high when set to output and sleep is asserted or FPGA VI is downloaded

The 9401 has a pull-up resistor causing this to happen.

Workaround:

Before going into sleep or downloading a new VI, set the outputs to inputs to prevent the glitch. 

Mounting/Unmounting a NI 9802 in Real-Time interrupts Scan Engine

When you take scan mode measurements and then mount and unmount the SD card, on the subsequent reads the scan mode I/O variable throws error -65536 until the FPGA VI is run.

Workaround:

Instead of the blank FPGA VI required to normally make this work, use an empty while loop inside the FPGA VI and leave this VI running while running the RT VI.

Reading Empty Target to Host DMA FIFO with Timeout Set to Zero Gradually Starves CPU in built LabVIEW RT executables on cRIO targets

In built LabVIEW RT applications on cRIO, if a Target to Host DMA FIFO read executes with a timeout of zero and the FIFO is empty a processor leak occurs that increases the CPU usage on the controller.

Workaround:

Read zero elements to find elements remaining, instead of using a zero timeout.

DMA from the host to the FPGA target on the cRIO-9002/9004

DMA is not supported from the host to the FPGA target on the cRIO-9002/9004.

LabVIEW returns an error if you try to output DMA from the cRIO-9002/9004.

Workaround:

None.

Known Issue

Abort and Reset Methods do not execute on incoming error

If an error is passed to either the Abort or Reset Methods, they will not execute and the error will be passed through.

Workaround:

Check, report, and clear errors manually in any error clusters wired to an Abort or Reset; otherwise, do not pass error clusters to these methods.

Cannot Deploy Scan Interface Modules or IO Variables  with Non-ASCII Characters

When deploying Scan Interface Modules or IO Variables with Non-ASCII characters such as Chinese or Japanese Characters it will report that the Deployment Completed with Errors.

Workaround:

Rename any Scan Interface Modules or IO Variables using Alpha Numeric  Characters.

Reading Empty Target to Host DMA FIFO with Timeout Set to Zero Gradually Starves CPU in built LabVIEW RT executables on cRIO targets

In built LabVIEW RT applications on cRIO, if a Target to Host DMA FIFO read executes with a timeout of zero and the FIFO is empty a processor leak occurs that increases the CPU usage on the controller.

Workaround:

Read zero elements to find elements remaining, instead of using a zero timeout.

NiRioScanInterface DMA Channel is listed when using Scan Interface along with LabVIEW FPGA Host Interface

When using Scan Inteface along with LabVIEW FPGA Host Interface, DMA FIFO method nodes display internal Scan Interface DMA Channels

Workaround:

None.

DMA from the host to the FPGA target on the cRIO-9002/9004

DMA is not supported from the host to the FPGA target on the cRIO-9002/9004.

LabVIEW returns an error if you try to output DMA from the cRIO-9002/9004.

Workaround:

None.