Known Issues
The following items are known issues in NI-RIO 3.4
|
ID |
Known Issue |
|
Known Issues with NI-RIO 3.4.0 and LabVIEW 2009 | |
| 197769 |
Using Windows Server 2003 R2 may require disabling Physical Address Extensions (PAE) Support for Windows Server 2003 R2 may require disabling Workaround—Disable PAE for Windows Server 2003 R2. Date Added—2/8/09 |
| 196284 |
NI-RIO 3.4 with LabVIEW 2009 causes network communication errors and will disconnect cRIO targets LabVIEW 2009 is not officially supported with NI-RIO 3.4, which adds support for LabVIEW 2009 SP1. If a target has the LabVIEW 2009 SP1 kernal on it, and you connect to the target from a Windows computer without LabVIEW 2009 SP1 (i.e. LabVIEW 2009) the console out will show “communications error has occurred” and then will disconnect from the target. Workaround—Upgrade to LabVIEW and LabVIEW Real-Time 2009 Service Pack 1. Date Added—2/8/09 |
| 198491 |
NI 9213 return bad first value when the module is inserted and is already running If an application is executing and the module is removed and readded, or a new module is added to the chassis while the code to read that module is already running, the first value returned is incorrect. Workaround—N/A Date Added—2/8/09 |
| 200550 |
Setting date/time in a tight loop causes the controller to run at an incorrect frequency If the date/time is being updated continuously in a loop with a period of less than 2 minutes, it can cause the controller to run slightly faster or slightly slower than it should Workaround—There is not a need to update the time this often. To avoid the issue described above, do not set the date/time in a loop, or set it much less frequently Date Added—2/8/09 |
| 184722 |
Mount SD Card (9802) Doesn't return error on Pharlap The NI 9802 is not supported on Pharlap targets (900x). If an attempt to mount the NI 9802 in LabVIEW Real-Time is made it will not work; however, no error is returned. The drive letter returned is “/” which is the only indication this didn’t work. Workaround—N/A
|
| 185187 |
Chassis settings don't automatically deploy Changes to the chassis properties are not automatically deployed. This is problematic when switching between Scan and FPGA Interface mode because it means the project can easily get out of sync with the target if the user does not manually deploy the chassis. Workaround—Manually deploy settings whenever changes are made to chassis properties.
|
| 195192 |
RIO Device Setup utility crashes after running a program with User-Defined variables on cRIO Once a VI is run with user-defined variables, subsequently running the RIO Device Setup will cause the target to become unresponsive. Workaround—Before running RIO Device Setup, (1) download a blank FPGA VI or (2) Reset the device.
|
| 193724 |
FPGA Discovery fails silently on sbRIO if FPGA is in a bad state Anytime the sbRIO is in the following states: safe mode, unconfigured IP address, or the NI-RIO driver is not installed on the controller, FPGA auto-discovery will fail silently. Note1 -- If the sbRIO controller is in a good state, auto-discovery succeeds. Workaround—Manually add the FPGA target
|
| 171345 |
Mounting/Unmounting a NI 9802 in Real-Time interrupts Scan Engine When you take scan mode measurements and then mount and unmount the SD card, on the subsequent reads the scan mode I/O variable throws error -65536 until the FPGA VI is run. Workaround—Instead of the blank FPGA VI required to normally make this work, use an empty while loop inside the FPGA VI and leave this VI running while running the RT VI. Date Added—11/25/09 |
| 177901 |
9401 output glitches high when set to output and sleep is asserted or FPGA VI is downloaded The 9401 has a pull-up resistor causing this to happen. Workaround—Before going into sleep or downloading a new VI, set the outputs to inputs to prevent the glitch
|
| 184171 |
cRIO-9074 set to Ethernet polling still uses interrupt based Ethernet When Ethernet polling is enabled on this controller it still gets interrupts anyway, causing jitter Workaround—N/A
|
| 196435 |
Configuring a module in scan mode that has been swapped for another without restarting causes error 1070 If a module being used in scan mode is swapped out and replaced, “Refresh Modules” command will pick up the difference; however, trying to programmatically configure the module results in “Error 1070” The module is implicitly opening a reference that is not being refreshed Workaround—(1) To programmatically prevent the issue, explicitly close both references (IO and module) by calling “Close Variable Connection” from the Shared Variables Palette, before running Discover IO.vi (2) If the VI is stopped and started again the references will be updated properly
|
| 132979 |
Reading Empty Target to Host DMA FIFO with Timeout Set to Zero Gradually Starves CPU in built LabVIEW RT executables on cRIO targets In built LabVIEW RT applications on cRIO, if a Target to Host DMA FIFO read executes with a timeout of zero and the FIFO is empty a processor leak occurs that increases the CPU usage on the controller. Date Added—01/15/2009 |
| 4K1CDCMA |
DMA from the host to the FPGA target on the cRIO-9002/9004 DMA is not supported from the host to the FPGA target on the cRIO-9002/9004. LabVIEW returns an error if you try to output DMA from the cRIO-9002/9004. Workaround—N/A |
|
KnownIssues with NI-RIO 3.4 and LabVIEW 8.6.x | |
| 116620 |
NiRioScanInterface DMA Channel is listed when using Scan Interface along with LabVIEW FPGA Host Interface When using Scan Inteface along with LabVIEW FPGA Host Interface, DMA FIFO method nodes display internal Scan Interface DMA Channels
|
| 4K1CDCMA |
DMA from the host to the FPGA target on the cRIO-9002/9004 DMA is not supported from the host to the FPGA target on the cRIO-9002/9004. LabVIEW returns an error if you try to output DMA from the cRIO-9002/9004. Workaround—N/A |
| -- |
Reading Empty Target to Host DMA FIFO with Timeout Set to Zero Gradually Starves CPU in built LabVIEW RT executables on cRIO targets In built LabVIEW RT applications on cRIO, if a Target to Host DMA FIFO read executes with a timeout of zero and the FIFO is empty a processor leak occurs that increases the CPU usage on the controller. Date Added—01/15/2009 |
| -- |
Cannot Deploy Scan Interface Modules or IO Variables with Non-ASCII Characters When deploying Scan Interface Modules or IO Variables with Non-ASCII characters such as Chinese or Japanese Characters it will report that the Deployment Completed with Errors. Date Added—01/15/2009 |
| -- |
Abort and Reset Methods do not execute on incoming error If an error is passed to either the Abort or Reset Methods, they will not execute and the error will be passed through Workaround---Check, report, and clear errors manually in any error clusters wired to an Abort or Reset; otherwise, do not pass error clusters to these methods Date Added—2/13/09 |
|
Known Issues with NI-RIO 3.4 and LabVIEW 8.5.x | |
| 4K1CDCMA |
DMA from the host to the FPGA target on the cRIO-9002/9004 DMA is not supported from the host to the FPGA target on the cRIO-9002/9004. LabVIEW returns an error if you try to output DMA from the cRIO-9002/9004. Workaround—N/A |
| -- |
VIs that use the calibration API should be modified to use the RIO Device I/O control Applications from versions of LabVIEW older than 8.5.x that use 783XR Calibration - Open FPGA VI Reference.vi should be updated to use the RIO Device I/O control instead of the VISA I/O control. Workaround—N/A |
| 40243 |
FPGA code generation into an existing host VI is very slow in FPGA Wizard If you use the FPGA Wizard to generate code, open the host VI, then generate code into the same VI, the code generation goes very slowly. Workaround—N/A |
| -- |
Large configuration files load slowly in FPGA Wizard Opening a large FPGA Wizard configuration file can take several minutes. Workaround—N/A |
| -- |
Maximum Timed I/O rate value is 70 kHz in FPGA Wizard generated code The maximum rate you can set for the Single Point Timed I/O timing engine on the Single Point Timed configuration page is 70 kHz. The maximum rate achievable varies with different hardware devices. Workaround—N/A |
| -- |
Selecting external clock requires external clock source with FPGA Wizard If you select External for the Clock Type on the Single Point Timed or Buffered DMA Input configuration page and you do not have an external clock source connected, LabVIEW appears to hang when you run the generated host VI. Press the Global Stop button to stop the VI or add an external clock source to resume running the VI. Workaround—N/A |
| -- |
NI-RIO 3.4 does not install support for the NI 987x serial modules for LabVIEW 8.5.x For serial module support in LabVIEW 8.5 download and install the C-Series Serial Software installer. NI-RIO 3.4 will install support for the NI 987x serial modules for LabVIEW 8.6.x, and later. Workaround—Install C-Series Serial Software from the installer linked above. Date Added—01/15/2009 |
|
KnownIssues with NI-RIO 3.4 and LabVIEW 8.2.x | |
| 4G3AED20 |
FPGA I/O Property Node returns wrong value for Module Model Code of NI 9217 module The FPGA I/O Property Node returns the value 9217, which is the Product ID, not the Module Model Code, of the NI 9217. The Module Model Code is 0x712B. Workaround—Look for 9217 in applications looking for the Product ID in LabVIEW 8.2.x Date Added—01/15/2008 |
| 4DAEDMLX |
Read/Write Controls execute more slowly after upgrade to NI-RIO 2.4.1 or later Read/Write Control now uses a Call Library Function Node to call the RIO driver. The Call Library Function Node executes additional code if debugging is enabled. To restore the performance to the original level, you must disable debugging in any VIs that contain Read/Write Controls. Workaround— You can disable debugging in a VI by going to File»VI Properties»Execution and unchecking Allow debugging. Date Added—01/15/2009 |
| 4K1CDCMA |
DMA from the host to the FPGA target on the cRIO-9002/9004 DMA is not supported from the host to the FPGA target on the cRIO-9002/9004. LabVIEW returns an error if you try to output DMA from the cRIO-9002/9004. Workaround—N/A |
| 3VKDOURY |
DMA in parallel While Loops If you use DMA in parallel While Loops either on the cRIO-9002/9004 or while accessing the FPGA target across a network, one of the While Loops might hang while the other executes. Workaround—N/A Date Added—01/15/2009 |