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Each issue appears as a row in the table and includes the following fields:
| ID | Known Issue | |||||
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| 383655 | ADC microport lines can be double driven momentarily The device's ADC and FPGA can momentarily double drive some ADC microport lines. The ADC microport is only tristated after CS_n and RD_n are deasserted AND the ADC detects a rising edge of the serial clock. When a read is performed, the clock is stopped prior to deasserting the CS and RD lines, which leaves the ADC actively driving the data bus. On a following write access, the host code enables the FPGA output driver prior to starting the ADC clock. During this period of time, the FPGA and ADC may drive into each other causing excessive current to flow. Workaround: Alter the ADC microport read/write VI to send an extra clock cycle with CS/RD/WT deasserted ('1') either immediately before or immediately after any write or read transaction to tell the ADC to stop driving the data bus.
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| 333614 | Issues with LabVIEW 2010 Real-Time If you are using LabVIEW 2010 and are deploying to a LabVIEW Real-Time target and you do not have the full version of LabVIEW Real-Time installed, your device may behave unexpectedly. Workaround: Download and install the LabVIEW Real-Time 2010 f1 Patch.
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| 137784 | Cannot save the ni5640R Spectrum Analyzer VI for previous versions of LabVIEW If you use LabVIEW 8.6 and try to save the ni5640 Spectrum Analyzer VI to a previous version of LabVIEW such as LabVIEW 8.5, warnings are returned. Workaround: N/A
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| 203715 | When you have enabled and chosen a CLIP for the DRAM socket, you cannot successfully compile when some Xilinx Options are all set to High When you have enabled and chosen a CLIP for the DRAM socket, you cannot successfully compile when the following Xilinx Options are all set to High: Synthesis Optimization Effort Level Map Overall Effort Level Place and Route Overall Effort Level Workaround: The Xilinx Options page in the FPGA Target Properties page is accessed by right-clicking the target in the Project Explorer window.
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| 239701 | RTSI lines 6 and 7 do not work RTSI lines 6 and 7 are not configurable. Workaround: N/A
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| 256974 | LabVIEW FPGA examples for the NI PCI-5640R and the NI PXIe-5641R are precompiled and configured only for a 32-bit Windows installation where they are installed under the default path, C:\Program Files\ The LabVIEW FPGA examples for the NI PCI-5640R and the NI PXIe-5641R are precompiled and configured for a 32-bit Windows installation where they are installed under C:\Program Files\. When installing to a non-default path or when installing on a 64-bit Windows machine (to C:\Program Files (x86)\), the host-side VI must be edited to correctly find the FPGA bitfile and bind its new path to the session typedef. The FPGA bitfiles do not need to be recompiled. Workaround: To configure the host-side VI to use the pre-compiled bitfile, complete the following steps: 1. Navigate to the example directory (installed at <LabVIEW>\examples\instr\ni5640R\FPGA\<Device Name>\<Example Name>) 2. Double-click <Example Name>.lvproj to open the project in LabVIEW. 3. Double-click <Example Name> (HOST).vi to open the host-side VI. 4. Open the block diagram for the <Example Name> (HOST).vi VI. Right-click the Open FPGA VI Reference VI and select Configure Open FPGA VI Reference. 5. Ensure the Bind FPGA host reference to type definition checkbox is selected and the path points to the NI-5640R VIs\ni5640R FPGA VI Reference.ctl file within the <Example Name> folder. 6. Click OK and wait for the type definition to update. 7. Select Save All.
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| 256976 | NI-5640R 1.3 and later includes a new FPGA I/O Node called DAC_Simultaneous_Reset that needs to be added to the target tree in older LabVIEW project files. NI-5640R 1.3 and later includes a new FPGA I/O Node called DAC_Simultaneous_Reset that needs to be added to the target tree in older LabVIEW project files. This node adds a new feature to the configuration loop that makes it easier to reset and synchronize the DACs. Workaround: To add this node to an older LabVIEW project file, complete the following steps: 1. Open the LabVIEW project. 2. Right-click the NI PCI-5640R target and select New»FPGA I/O. 3. Under Available Resources, select Configuration»DAC_Simultaneous_Reset. 4. Click Add. 5. Click OK.
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| 257253 | Cannot find FPGA Examples LabVIEW FPGA examples cannot be located using the NI Examples Finder. Workaround: To locate these examples, refer to the table in the Installed Files section of NI-5640R Readme or navigate to Start»All Programs»National Instruments»NI-5640R»Examples»<LabVIEW> and then open the FPGA folder.
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| 257263 | Global variables stored in different locations Register and Circular Buffer data exchange policies use global variables created by the generated code behind the NI-5640R Asynchronous Programming nodes. If your LabVIEW project has not yet been saved, the global variables are stored on disk in a folder at <LabVIEW>\instr.lib\ni5640R\FPGA\AsyncWires\Globals. After your project is saved, the global variables are stored in a folder named Globals in the same folder where your project is stored. The globals are also placed in a LabVIEW project folder named Generated Globals. Deleting a global from the disk folder breaks the primitives that use it, but does not affect the bitfile produced by a previous compile. Causing that primitive to reconfigure itself also causes it to regenerate the globals. Workaround: N/A
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| 257592 | Host VIs do not open Host VIs developed in previous versions of LabVIEW do not run when initially opened in later versions of LabVIEW. For example, if you created a host VI in LabVIEW 8.2.1, the VI does not run when initially opened in any later version of LabVIEW such as LabVIEW 8.5, 8.6, 2009, or 2010. Similarly, if you created a host VI in LabVIEW 8.6, the VI does not run when initially opened in any later version of LabVIEW such as LabVIEW 2009, or 2010. Workaround: To run the VI, complete the following steps: 1. Verify that LabVIEW is closed, and then copy the folder <LabVIEW>\examples\instr\ni5640R\FPGA\ni5640R Template\NI-5640R VIs over your project folder of the same name. 2. Copy <LabVIEW>\examples\instr\ni5640R\FPGA\ni5640R Template\ni5640R Template.lvlib to your project folder. 3. Open the copied ni5640R Template.lvlib. 4. Select Save As, then click Rename in the dialog box. 5. Rename ni5640R Template.lvlib to match the name of the original library.
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Contact NI regarding this document or issues in the document. If you contact NI in regards to a specific issue, reference the ID number given in the document. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting NI). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Also contact us if you find a workaround for an issue that is not listed in the document.