AI Convert Clock Signal Behavior for Analog Input Modules

Scanned TestScale analog input modules contain a single A/D converter (ADC) and a multiplexer to select between multiple input channels. When the TestScale Module Interface receives a SampleClock pulse, it begins generating a Convert Clock for each scanned module in the current task. Each Convert Clock signal the acquisition of a single channel from that module. The ConvertClock rate depends on the module being used, the number of channels used on that module, and the system Sample Clock rate.

The driver chooses the fastest conversion rate possible based on the speed of the A/D converter for each module and adds 10 μs of padding between each channel to allow for adequate settling time. This scheme enables the channels to approximate simultaneous sampling. If the AI Sample Clock rate is too fast to allow for 10 μs of padding, NI-DAQmx selects a conversion rate that spaces the AI Convert Clock pulses evenly throughout the sample. NI-DAQmx uses the same amount of padding for all the modules in the task. To explicitly specify the conversion rate, use the ActiveDevs and AI Convert Clock Rate properties using the DAQmx Timing property node or functions.