Creating the LabVIEW FPGA Code for the Coprocessor Harness

Before getting started, copy the contents of <LabVIEW>\examples\RTG\Coprocessor\Passthrough\<coprocessor> folder into the folder you will use for the custom code efforts. Rename both the project and the VI as desired.

Understanding Project Configuration

The project contains several resources required for a successful compilation:

  • Clocks—Three clocks are provided:
    • 160 MHz Clock (derived from PXIe_Clk100): Used as the clock for all signal processing. The VST runs at 156.25 MHz. This coprocessor signal processing needs to run slightly faster at 160 MHz to ensure there are no underflows of data due to Aurora protocol overhead. The signal processing must be written so that it can run faster than the VST.
    • Register Bus Clock (40 MHz, derived from PXIe_Clk100): The data source and sink modules used to transfer data from/to the VST use the Instruction Framework to communicate with the host (Windows) application. Custom modules can also use the Instruction Framework if desired.
    • 80 MHz Clock: Configuring the MGT links used for the Aurora protocol that transfer data between the VST and the coprocessor require an 80 MHz clock for configuration and monitoring.
  • FIFOs—The Instruction Framework requires a DMA FIFO with a fixed name and configuration as follows:
    • Name: reg.host instruction fifo 0
    • Type: Host to Target – DMA
    • Size: 1023 Elements
    • Data Type: U64
    • Number of Elements Per Read: 1
  • Aurora 64B/66B CLIP—Sets up the Aurora protocol to using the MGTs connected to the coprocessor FPGA. The CLIP can be found in <Program Files>\National Instruments\Shared\FPGA\CLIP\<coprocessor>.

    • Software Components

    The following components are important in creating and understanding the LabVIEW FPGA code.