Adding the Socketed CLIP to a LabVIEW Project (FPGA Module)

Before you begin, ensure that you have installed your hardware into the chassis and completed the steps in Installing the Software.

Add a component-level IP (CLIP) item to the LabVIEW project to instantiate the CLIP inside the FPGA.

1. Create and save a new LabVIEW project (for example, My7903Clip.lvproj).
2. Add an FPGA target that supports CLIP to the project.
3. Right-click the FPGA target and select Properties from the shortcut menu to display the FPGA Target Properties dialog box.
4. Select Component-Level IP from the Category list to display the Component-Level IP Properties page.
5. Click Add, select the declaration XML file for the socketed clip, and then click OK.
   Note The CLIP wizard automatically adds the declaration XML file to the project.
6. Click OK to close the FPGA Target Properties dialog box.
7. In the Project Explorer window, right-click the IO Socket under the FPGA target, and select Properties from the shortcut menu.
8. On the General page of the IO Socket Properties dialog box, select the socketed CLIP to instantiate.
9. On the Clock Selections page, select the appropriate clocks for the CLIP. Clock selections will vary depending on CLIP requirements.
10. Click OK. Notice that the Project Explorer window now includes socketed CLIP under the IO Socket, as well as the I/O defined in the declaration XML file.