PXIe-7890 Specifications
- Updated2024-12-11
- 15 minute(s) read
PXIe-7890 Specifications
Definitions
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.
Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
- Typical specifications describe the performance met by a majority of models.
- Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.
- Measured specifications describe the measured performance of a representative model.
Specifications are Typical unless otherwise noted.
Conditions
Specifications are valid under the following conditions unless otherwise noted.
- Ambient temperature of 0 °C to 55 °C .
- Installed in chassis with slot cooling capacity ≥58 W.
Front Panel
Connector
Pinouts
PORT 0 and PORT 1
The following image shows the pinout for the PORT 0 and PORT 1 QSFP connectors.
Pin | Description |
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Txn <1..4> | Transmitter Inverted Data Input |
Txp <1..4> | Transmitter Non-Inverted Data Input |
Rxn <1..4> | Receiver Inverted Data Output |
Rxp <1..4> | Receiver Non-Inverted Data Output |
SCL | 2-Wire Serial Interface Clock |
SDA | 2-Wire Serial Interface Data |
ModPrsL | Module Present |
ModSelL | Module Select |
ResetL | Module Reset |
IntL | Interrupt |
LPMode | Low Power Mode |
Vcc Rx | +3.3 V Power Supply Receiver |
Vcc Tx | +3.3 V Power Supply Transmitter |
Vcc1 | +3.3 V Power Supply |
GND | Ground |
CONNECTOR 0 and CONNECTOR 4
The following image shows the pinouts for CONNECTOR 0 and CONNECTOR 4.
Pin | Description | Signal Name in LabVIEW |
---|---|---|
DIO <0..31> |
Bidirectional digital input/output signal connection |
Digital Input:
Digital Output:
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EXTCLKIN |
External clock input source that can be used for source synchronous acquisitions; the provided clock source must be stable and glitch free |
Conn 0 External Clock Conn 4 External Clock |
GND |
Ground reference for digital signals |
— |
NC |
No connection |
— |
CONNECTOR 1 and CONNECTOR 3
The following image shows the pinout for CONNECTOR 1 and CONNECTOR 3.
Pin | Description | Signal Name in LabVIEW |
---|---|---|
AO <0..15> (PXIe-7890) AO <0..31> (PXIe-7891) |
Analog output signal connection |
PXIe-7890:
PXIe-7891:
|
GND | Ground reference for the analog output signal | — |
NC | No Connection | — |
CONNECTOR 2
The following image shows the pinout for CONNECTOR 2, the analog input VHDCI front panel connector.
Pin | Description | Signal Name in LabVIEW |
---|---|---|
AI <0+...7+> (PXIe-7890) AI <0+...15+> (PXIe-7891) |
Positive analog input signal connection |
PXIe-7890:
PXIe-7891:
|
AI <0-...7-> (PXIe-7890) AI <0-...15-> (PXIe-7891) |
Negative analog input signal connection | |
GND | Ground reference for the analog input signal | — |
NC | No connection | — |
Port 0 and Port 1
Connector | QSFP, SFF-8436 compliant |
Data rate | 500 Mbps to 5 Gb/s |
Number of lanes | 8 RX/TX (GTH) |
Supported high-speed cable type | Electrical/ optical |
Optical cable power | 3.3 V ±5%, 1 A per port |
Multi-Gigabit Transceiver (MGT)
MGT TX± Channels
MGT RX± Channels
Differential input voltage range at ≤ 6.6 Gb/s | 150 mV pk-pk to 2000 mVpk-pk , nominal |
MGT Reference Clock Generator
Supported generated frequencies | 60.000 MHz to 385.714 MHz 400.000 MHZ to 450.000 MHz 480.000 MHz to 675.000 MHz 685.714 MHz to 771.428 MHz 800 MHz |
Clocking resources | PXIe_CLK100 |
Available MGT Reference Clocks | 4 |
Connector 0 and Connector 4
The following section describes the digital input and output characteristics accessible through CONNECTOR 0 and CONNECTOR 4.
CONNECTOR 0 and CONNECTOR 4 are identical and share the same pinout, but are oriented in opposite directions on the module. For more information, including pinout descriptions, refer to the PXIe-7890/7891 Getting Started content in the NI Product Documentation Center.
Connectors 0 and 4 | 68-pin VHDCI receptacle |
Digital I/O
Number of channels | 64 | ||||||
Signal type | Single-ended | ||||||
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Direction control | Per channel | ||||||
Latency | 25 ns | ||||||
Power-on-state | Digital input | ||||||
Number of external clock input | 2 | ||||||
Protection | ±15 V per line, up to two lines simultaneously |
Voltage Family | Input Low Voltage (VIL) Maximum | Input High Voltage (VIH) Minimum |
---|---|---|
3.3 V | 0.80 V | 2.00 V |
5.0 V | 1.50 V | 3.50 V |
Minimum input voltage | 0 V |
Maximum input voltage | 5 V |
Input impedance | 100 kΩ, pull-down |
Voltage Family | Current | Output Low Voltage (VOL) Maximum | Output High Voltage (VOH) Minimum |
---|---|---|---|
3.3 V | 100 µA | 0.10 V | 3.20 V |
4 mA | 0.45 V | 2.85 V | |
5 V | 100 µA | 0.10 V | 4.90 V |
4 mA | 0.45 V | 4.55 V |
Maximum DC output current per channel | 4.0 mA (sink or source) |
Output impedance | 50 Ω ± 20% |
Maximum output toggle rate | 10 MHz |
Connector 1
The following section describes the analog output characteristics accessible through CONNECTOR 1. For more information, including pinout descriptions, refer to PXIe-7890/7891 Getting Started content in the NI Product Documentation Center.
Connector type | 68-pin VHDCI receptacle |
Analog Output
Output type | Single-ended, voltage output | ||||||||
Number of channels | 16 | ||||||||
Resolution | 16 bits | ||||||||
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Analog latency | 75 nsec | ||||||||
Maximum update rate | 2 MS/s | ||||||||
INL | ±0.5 LSB typical, ±2 LSB maximum | ||||||||
DNL | ±0.5 LSB typical, ±1 LSB maximum | ||||||||
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Output coupling | DC | ||||||||
Output impedance | 0.3 Ω | ||||||||
Gain drift | 5.5 ppm/˚C | ||||||||
Offset drift | 30 μV/˚C | ||||||||
Slew rate | 20 V/µs | ||||||||
Noise (DC to 612 kHz) | 70 μVrms | ||||||||
Current drive | ±15 mA | ||||||||
Protection | Short circuit to ground | ||||||||
Crosstalk @100 kHz | -85 dB | ||||||||
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Power-on output state | 0 V | ||||||||
Power-on glitch | 640 mV, decays to 0 V in 860 µs | ||||||||
Power-off glitch | 1.4 V, decays to 0 V in 200 µs | ||||||||
Glitch during module reset | 1.4 V, decays to 0 V in 200 µs |
Step Size | Accuracy | |
---|---|---|
±10 V | ±16 LSB | ±2 LSB |
3.0 µs | 7.4 µs |
Nominal Range | Condition | Gain Error (Percent of Reading) | Offset Error |
---|---|---|---|
±10 V | Typical (25°C to ±5°C) | ±0.016% | ±0.11 mV |
Maximum (0°C to 55°C) | ±0.070% | 1.79 mV |
Nominal Range | Condition | Gain Error (Percent of Reading) | Offset Error |
---|---|---|---|
±10 V | Typical (25°C to ±5°C) | ±0.096% | ±2.73 mV |
Maximum (0°C to 55°C) | ±0.219% | ±8.86 mV |
AO Absolute Accuracy Equation
The following example calculates the absolute full scale calibrated accuracy at 25 ±5˚C on the 10 V range.
Connector 2
The following section describes the analog input characteristics accessible through CONNECTOR 2. For more information, including pinout descriptions, refer to PXIe-7890/7891 Getting Started content in the NI Product Documentation Center.
Connector type | 68-pin VHDCI receptacle |
Analog Input
Number of channels | 8 | ||||||||||||||||||||
Input mode | Differential | ||||||||||||||||||||
Type of ADC | Successive approximation register (SAR) | ||||||||||||||||||||
Resolution | 16 bits | ||||||||||||||||||||
Input ranges | ±20 V, ±10 V, ±5 V, ±2 V, ±1 V | ||||||||||||||||||||
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Maximum rate (per channel) | 2 MS/s | ||||||||||||||||||||
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Input coupling sampling | DC | ||||||||||||||||||||
Input bias current | ±5 nA | ||||||||||||||||||||
Input offset current | ±5 nA | ||||||||||||||||||||
INL | ±6 LSB typical, ±12.7 LSB maximum | ||||||||||||||||||||
DNL | ±0.4 LSB typical, ±1 LSB maximum | ||||||||||||||||||||
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Crosstalk (100 kHz) into 50 Ω | -70 dB | ||||||||||||||||||||
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Specification | Nominal Range | ||||
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±20 V | ±10 V | ±5 V | ±2 V | ±1 V | |
Input noise (μVrms) | 1600 | 670 | 340 | 140 | 80 |
Gain drift (ppm/˚C) | 22.6 | 16.7 | |||
Offset drift (μV/˚C) | 64.0 | 29.2 | 14.9 | 6.5 | 3.8 |
Typical input range, AI+ to AI- (V) | ±20.62 | ±10.22 | ±5.11 | ±2.04 | ±1.02 |
Minimum input range, AI+ to AI- (V) | ±20.38 | ±10.16 | ±5.08 | ±2.03 | ±1.01 |
Maximum Working Voltage (V) (Signal + Common Mode to Ground) | ±22 | ±13 | ±10.5 | ±9.0 | ±8.5 |
Nominal Range | Condition | Gain Error (Percent of Reading) | Offset Error |
---|---|---|---|
±20 V | Typical (25°C ± 5°C) | ±0.038% | ±1.44 mV |
Maximum (0°C to 55°C) | ±0.278% | ±5.94 mV | |
±10 V | Typical (25°C ± 5°C) | ±0.032% | ±0.71 mV |
Maximum (0°C to 55°C) | ±0.215% | ±2.04 mV | |
±5 V | Typical (25°C ± 5°C) | ±0.032% | ±0.36 mV |
Maximum (0°C to 55°C) | ±0.215% | ±1.05 mV | |
±2 V | Typical (25°C ± 5°C) | ±0.032% | ±0.15 mV |
Maximum (0°C to 55°C) | ±0.215% | ±0.47 mV | |
±1 V | Typical (25°C ± 5°C) | ±0.032% | ±0.08 mV |
Maximum (0°C to 55°C) | ±0.215% | ±0.27 mV |
Nominal Range | Condition | Gain Error (Percent of Reading) | Offset Error |
---|---|---|---|
±20 V | Typical (25°C ± 5°C) | ±0.143% | ±3.10 mV |
Maximum (0°C to 55°C) | ±0.808% | ±22.80 mV | |
±10 V | Typical (25°C ± 5°C) | ±0.139% | ±0.98 mV |
Maximum (0°C to 55°C) | ±0.536% | ±6.89 mV | |
±5 V | Typical (25°C ± 5°C) | ±0.142% | ±0.54 mV |
Maximum (0°C to 55°C) | ±0.546% | ±3.67 mV | |
±2 V | Typical (25°C ± 5°C) | ±0.142% | ±0.28 mV |
Maximum (0°C to 55°C) | ±0.546% | ±1.74 mV | |
±1 V | Typical (25°C ± 5°C) | ±0.142% | ±0.19 mV |
Maximum (0°C to 55°C) | ±0.546% | ±1.09 mV |
AI Absolute Accuracy Equation
The following example calculates the absolute full scale calibrated accuracy at 25 ±5˚C on the 20 V range with 10,000 readings and 3δ coverage factor.
Connector 3
The following sections describe the low-latency analog output characteristics accessible through CONNECTOR 3. For more information, including pinout descriptions, refer to PXIe-7890/7891 Getting Started content in the NI Product Documentation Center.
Connector type | 68-pin VHDCI receptacle |
Low-Latency Analog Output
Output type | Single-ended, voltage output | ||||||
Number of channels | 16 | ||||||
Resolution | 16 bits | ||||||
Output range | ±10 V, ±0.5 V[3]3 The PXIe-7890 supports 0.5 V range only on Ch<0..7>. | ||||||
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Analog latency | 50 nsec | ||||||
Maximum update rate | 4 MS/s | ||||||
INL | ±4 LSB maximum | ||||||
DNL | ±1 LSB maximum | ||||||
Output coupling | DC | ||||||
Output impedence | 50 Ω | ||||||
Slew rate | 320 V/µs | ||||||
Current drive | ±100 mA | ||||||
Crosstalk @100 kHz | -78 dB | ||||||
Protection | Short circuit to ground | ||||||
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Power on state | 0 V | ||||||
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Settling time at Full Scale to 16 LSB | 1.2 µs |
Specification | Nominal Range | |
---|---|---|
±10 V | ±0.5 V | |
Output Noise (μVrms) – DC to 612 kHz | 78 | 16 |
Gain Drift (ppm/˚C) | 13 | 78 |
Offset Drift (μV/˚C) | 260 | 13 |
Typical Output Range (V) | ±10.32 | ±0.51 |
Minimum Output Range (V) | ±10.15 | ±0.50 |
Information in Table 14. Low-Latency Analog Output Calibrated Accuracy and Table 15. Low-Latency Analog Output Uncalibrated Accuracy is applicable only for high impedance loads (> 1 Mohm), in which the load current is negligible due to the 50 ohm source resistance.
Nominal Range | Condition | Gain Error (Percent of Reading) | Offset Error |
---|---|---|---|
±10 V | Typical (25°C to ±5°C) | ±0.028% | ±2.67 mV |
Maximum (0°C to 55°C) | ±0.162% | ±19.94 mV | |
±0.5 V | Typical (25°C to ±5°C) | ±0.099% | ±0.13 mV |
Maximum (0°C to 55°C) | ±0.852% | ±1.03 mV |
Nominal Range | Condition | Gain Error (Percent of Reading) | Offset Error |
---|---|---|---|
±10 V | Typical (25°C to ±5°C) | ±0.256% | ±24.42 mV |
Maximum (0°C to 55°C) | ±0.828% | ±81.65 mV | |
±0.5 V | Typical (25°C to ±5°C) | ±1.164% | ±1.22 mV |
Maximum (0°C to 55°C) | ±4.319% | ±4.21 mV |
Low Latency AO Absolute Accuracy Equation
The following example calculates the absolute full scale calibrated accuracy at 25 ±5˚C on the 10 V range.
Calibration
Interval | 2 years |
Reconfigurable FPGA
The PXIe-7890 provides a KU060 FPGA with characteristics shown in the following table.
Characteristics | KU060 |
---|---|
LUTs | 331,680 |
DSP48 slices (25 × 18 multiplier) | 2,760 |
Embedded Block RAM | 38.0 Mb |
Timebase reference sources | PXI Express 100 MHz (PXIe_CLK100) |
Data transfers | DMA, interrupts, programmed I/O, multi-gigabit transceivers |
Number of DMA channels | 60 |
Onboard DRAM
Memory size | 4 GB (2 banks of 2 GB) |
DRAM clock rate | 1064 MHz |
Physical bus width | 32 bit |
LabVIEW FPGA DRAM clock rate | 267 MHz |
LabVIEW FPGA DRAM bus width | 256 bit per bank |
Maximum theoretical data rate | 17 GB/s (8.5 GB/s per bank) |
Bus Interface
Form factor | PCI Express Gen-3 x8 |
Maximum Power Requirements
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Power consumption is from both PXI Express backplane power connectors.
Physical Characteristics
Dimensions (not including connectors) | 4.0 cm × 13.0 cm × 21.6 cm (0.8 in. × 5.1 in. × 8.5 in.) |
Weight | 771 g (27.2 oz) |
Environmental Characteristics
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Pollution Degree | 2 | ||||||||
Maximum altitude | 2,000 m (800 mbar) (at 25 °C ambient temperature) | ||||||||
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1 800 mV pk-pk when transmitter output swing is set to the maximum setting.
2 Only valid for fault on +/- input for 8 AI channels maximum. Degrades to +/-30 V for all 16 channels fault.
3 The PXIe-7890 supports 0.5 V range only on Ch<0..7>.
4 AO channel will shut down at fault voltage more than ±5 V from configured AO output.