PXIe-6570 Specifications
- Updated2023-02-20
- 12 minute(s) read
PXIe-6570 Specifications
These specifications apply to the PXIe-6570. When using the PXIe-6570 in the Semiconductor Test System, refer to the Semiconductor Test System Specifications.
Definitions
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty. Warranted specifications account for measurement uncertainties, temperature drift, and aging. Warranted specifications are ensured by design or verified during production and calibration.
The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
- Typical specifications describe the performance met by a majority of models.
- Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.
Conditions
Specifications are valid under the following conditions unless otherwise noted.
- Operating temperature of 0 °C to 45 °C
- Operating temperature within ±5 ºC of the last self-calibration temperature
- Recommended calibration interval of 1 year. The PXIe-6570 will not meet specifications unless operated within the recommended calibration interval.
- DUT Ground Sense (DGS) same potential as the Ground (GND) pins
Note The DGS feature is only available on PXIe-6570 module revisions 158234C-xxL or later.
- Chassis fans set to the highest setting if the PXI Express chassis has multiple fan speed settings
- 30-minute warmup time before operation
General
Channel count | 32 | ||||||
| |||||||
System channel count[1] | 256 | ||||||
Large Vector Memory (LVM) | 128M vectors | ||||||
| |||||||
Maximum allowable offset (DGS minus GND) | ±300 mV | ||||||
Supported measurement range[2] | -2 V to 7 V[3] |
Timing
Vector Timing
Maximum vector rate | 100 MHz | ||||||||
Vector period range | 10 ns to 40 µs (100 MHz to 25 kHz) | ||||||||
Vector period resolution | 38 fs | ||||||||
|
Clocking
Master clock source | PXIe_CLK100[4] |
Sequencer clock domains | One (independent sequencer clock domains on a single instrument not supported) |
Drive and Compare Formats
Pin Data States
Pin States
- 0 — Drive zero.
- 1 — Drive one.
- L — Compare low.
- H — Compare high.
- X — Do not drive; mask compare.
- M — Compare midband, not high or low.
- V — Compare high or low, not midband; store results from capture functionality if configured.
- D — Drive data from source functionality if configured.
- E — Expect data from source functionality if configured.[7]
- - — Repeat previous cycle. Do not use a dash (-) for the pin state on the first vector of a pattern file unless the file is used only as a target of a jump or call operation.
Edge Timing
Edge Types
| |||||||
| |||||||
Number of time sets[8] | 31 |
Edge Generation Timing
| |||||||||||||||||||
| |||||||||||||||||||
Edge placement resolution | 39.0625 ps | ||||||||||||||||||
| |||||||||||||||||||
| |||||||||||||||||||
| |||||||||||||||||||
TDR deskew adjustment resolution | 39.0625 ps |
Driver, Comparator, Load
Driver
Signal type | Single-ended, referenced to the DGS pin when connected. Otherwise referenced to GND. | ||||||||||
Programmable levels | VIH, VIL, VTERM | ||||||||||
| |||||||||||
Maximum DC drive current | ±32 mA | ||||||||||
Output impedance | 50 Ω | ||||||||||
Rise/fall time, 20% to 80% | 1.2 ns, up to 5 V |
Comparator
Signal type | Single-ended, referenced to the DGS pin when connected. Otherwise referenced to GND. | ||||||||
Programmable levels | VOH, VOL | ||||||||
| |||||||||
Programmable input termination modes | High Z, 50 Ω to VTERM, Active Load | ||||||||
Leakage current | <15 nA, in the High Z termination mode |
Active Load
Programmable levels | IOH, IOL | ||||||||
| |||||||||
|
PPMU
PPMU Force Voltage
Signal type | Single-ended, referenced to the DGS pin when connected. Otherwise referenced to GND. | ||||||||||||||||||||
|
PPMU Measure Voltage
Signal type | Single-ended, referenced to the DGS pin when connected. Otherwise referenced to GND. | ||||||||
|
PPMU Force Current
How to Calculate PPMU Force Current Accuracy
Range | Resolution | Accuracy |
---|---|---|
±2 µA | 60 pA | ±1% of range for Zone 1 of Figure 3, warranted |
±32 µA | 980 pA | |
±128 μA | 3.9 nA | |
±2 mA | 60 nA | |
±32 mA | 980 nA |
- Specify the desired forced current.
- Based on the desired forced current, select an appropriate current range from Table 1.
- Divide the desired forced current from step 1 by the current range from step 2 and multiply by 100 to calculate the Percent of Current Range Forced.
- Based on the impedance of the load, calculate the voltage required to force the desired current from step 1. Use the following equation: Voltage Required = Desired Current * Load Impedance.
- Using Figure 2, locate the zone in which the Percent of Current Range Forced calculated in step 3 intersects with the Voltage calculated in step 4. If the intersection is outside of Zone 1, then there are no warranted specs. To get warranted specs, the current range and/or forced current must be adjusted until the intersection is in Zone 1.
- Based on the zone found in step 5, use Table 1 to calculate the accuracy of the forced current.
|
PPMU Measure Current
How to Calculate PPMU Measure Current Accuracy
Range | Resolution | Accuracy |
---|---|---|
±2 μA | 460 pA |
±1% of range for Zone 1 of Figure 4, warranted ±1.5% of range for Zone 2 of Figure 4, warranted |
±32 μA | 7.3 nA | |
±128 μA | 30 nA | |
±2 mA | 460 nA | |
±32 mA | 7.3 μA |
- Specify the desired measured current.
- Based on the desired measured current, select an appropriate current range from Table 2.
- Divide the desired measured current from step 1 by the current range from step 2 and multiply by 100 to calculate the Percent of Current Range Measured.
- If forcing voltage and then measuring current, Voltage in Figure 3 is equal to the forced voltage. If forcing current and then measuring current, Voltage in Figure 3 is equal to the voltage required to force the desired current based on the impedance of the load. Use the following equation: Voltage Required = Desired Current * Load Impedance.
- Using Figure 3, locate the zone in which the Percent of Current Range Measured calculated in step 3 intersects with the Voltage calculated in step 4. If the intersection is outside of Zone 1 or Zone 2, then there are no warranted specs. To get warranted specs, the current range and forced current or forced voltage must be adjusted until the intersection is in Zone 1 or Zone 2.
- Based on the zone found in step 5, use Table 2 to calculate the accuracy of the measured current.
PPMU Programmable Aperture Time
|
Pattern Control
Opcodes
Refer to the following table for supported opcodes. Using matched and failed opcode parameters with multiple PXIe-6570 instruments requires the PXIe-6674T synchronization module. Other uses of flow-control opcodes with multiple PXIe-6570 instruments only require NI-TCLK synchronization.
Category | Supported Opcodes |
---|---|
Flow Control |
|
Sequencer Flags and Registers |
|
Signal |
|
Digital Source and Capture |
|
Pipeline Latencies
Minimum delay between source_start opcode and the first source opcode or subsequent source_start opcode | 3 μs |
Matched and failed condition pipeline latency | 80 cycles |
Source and Capture
Independent Clock Generators
Number of Clock Generators | 32 (one per pin) |
Clock Period Range | 6.25 ns to 40 us (160 MHz to 25 kHz)[12] |
Clock Period Resolution | 38 fs |
Frequency Measurements
|
Calculating Frequency Counter Error
Use the following equation to calculate the frequency counter error (ppm).
where
- MeasurementTime is the time, in seconds, over which the frequency counter measurement is configured to run
- UnknownClockPeriod is the time, in seconds, of the period of the signal being measured
- TBerr is the error of the Clk100 timebase
Refer to the following table for a few examples of common Clk100 timebase accuracies.
PXI Express Hardware Specification Revision 1.0 | PXIe-1085 Chassis | PXIe-6674T Override |
---|---|---|
100 µ (100 ppm) | 25 µ (25 ppm) | 80 n (80 ppb) |
Example 1: Calculating Error with a PXIe-1085 Chassis
Calculate the error of performing a frequency measurement of a 10 MHz clock (100 ns period) with a 1 ms measurement time using the PXIe-Clk100 provided by the PXIe-1085 chassis as the timebase.
Solution
Example 2: Calculating Error when Overriding with the PXIe-6674T
Calculate the error if you override the PXIe-Clk100 timebase with the PXIe-6674T and increase the measurement time to 10 ms.
Solution
Calibration Interval
Recommended calibration interval | 1 year |
Physical Characteristics
PXIe slots | 2 |
Dimensions | 131 mm × 42 mm × 214 mm (5.16 in. × 1.65 in. × 8.43 in.) |
Weight | 920 g (32.45 oz.) |
Power Requirements
The PXIe-6570 draws current from a combination of the 3.3 V and 12 V power rails. The maximum current drawn from each of these rails can vary depending on the PXIe-6570 mode of operation. The total power consumption will not exceed the input power specification.
Input power | 68 W | ||||||
|
1 The system channel count is the maximum number of channels available when using multiple PXIe-6570 instruments in a single chassis as a digital subsystem. Some functionality described in this document requires that a PXIe-6674T synchronization module be used in conjunction with each digital subsystem.
2 If the total voltage sourced or driven on any pin relative to GND exceeds the supported measurement range, instrument performance may be degraded.
3 Voltages > 6 V require the Extended Voltage Range mode of operation.
4 Sourced from chassis 100 MHz backplane reference clock, external 10 MHz reference, or PXIe-6674T.
5 When using NI-Digital 18.0 and later, the maximum vector rate for patterns may be limited by the pulse width requirements, which may not allow all formats and edge multipliers to be used up to the fastest vector rate.
6 The SBC format is not supported within the 2x edge multiplier mode.
7 This functionality requires NI-Digital 18.0 or later.
8 31 time sets can be configured. One additional time set, represented by a -, repeats the previous time set.
9 For specifications in a Semiconductor Test System, refer to the Semiconductor Test System Specifications.
10 The Extended Voltage Range is an unwarranted mode of operation that allows the PMU to force voltages between 6 V and 7 V for applications that can tolerate more error than the normal force voltage accuracy.
11 To learn how to calculate achievable data rates for Digital Source or Digital Capture, visit ni.com/info and enter the info code DigitalSourceCapture to access the Calculating Digital Source Rate tutorial or the Calculating Digital Capture Rate tutorial.
12 Clocks with a period < 7.5 ns will have a non-50% duty cycle.