DIGITAL I/O (DIO)

The PXIe-5841 DIGITAL I/O (DIO) connector supports eight parallel LVCMOS lines in addition to four lanes of high speed serial multi-gigabit transceivers (MGT), using a 42-pin Molex Nano-Pitch I/O connector. The eight LVCMOS lines support 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage levels and can be used in a variety of applications including serial peripheral interface bus (SPI), inter-integrated circuit (I2C) bus, and digital triggering and events. You can control the lines directly from the instrument's onboard FPGA.

The PXIe-5841 DIGITAL I/O (DIO) can use DIO signals in a variety of applications including serial peripheral interface bus (SPI), inter-integrated circuit (I2C) bus, and digital triggering and events.

Signal Type Direction Description
MGT Tx± <3..0> Xilinx Virtex-7 GTH Output Dedicated MGT transmit differential pairs (AC-coupled).
MGT Rx± <3..0> Input Dedicated MGT receive differential pairs (AC-coupled).
MGT REF± Differential User reference clock source for Virtex-7 GTH banks. This clock is multiplexed with DIO <1..0> at the connector. The reference clock function and the DIO function of these pins cannot be used at the same time.
DIO <1..0> Single-ended Bidirectional Single data rate (SDR) is default. Double data rate (DDR) can be achieved using user-supplied component-level IP (CLIP) or IP integration node. DIO <1..0> are multiplexed with a user-supplied MGT reference clock. The DIO and reference clock functions cannot be used at the same time.
DIO <7..2>
5.0 V DC Output Single-ended LVCMOS digital lines. 5.0 V power source, off by default.
Note Refer to the PXIe-5841 Specifications document available at ni.com/manuals for the voltage and current capabilities.
GND Ground — Connector ground.