The ADC and DAC are clocked at 1.25 GS/s to provide up to 1 GHz of complex bandwidth, and high-resolution I/Q data rates are achieved by using the Fractional Interpolator and Fractional Decimator DSP FPGA VIs. The ADC and DAC are automatically synchronized to the Data Clock domain inside the FPGA, which allows for interfacing to both the ADC and DAC in the same clock domain with full synchronization.