The PXIe-1095 chassis supplies PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 to every peripheral slot with an independent driver for each signal. The following figure shows the chassis reference clock architecture.

An independent buffer (having a source impedance matched to the backplane and a skew of less than 250 ps between slots) drives PXI_CLK10 to each slot. You can use this common reference clock signal to synchronize multiple modules in a measurement or control system.

An independent buffer drives PXIe_CLK100 to each peripheral slot. These clocks are matched in skew to less than 100 ps. The differential pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_CLK100 so that when there is no peripheral or a peripheral that does not connect to PXIe_CLK100, there is no clock being driven on the pair to that slot. Refer to the following figure for a termination example.

An independent buffer drives PXIe_SYNC100 to each peripheral slot. The differential pair must be terminated on the peripheral with LVPECL termination for the buffer to drive PXIe_SYNC100 so that when there is no peripheral or a peripheral that does not connect to PXIe_SYNC100, there is no SYNC100 signal being driven on the pair to that slot.

The backplane uses a 100 MHz Voltage-Controlled Crystal Oscillator (VCXO) to directly create PXIe_CLK100 and does a divide-by-10 to create PXI_CLK10. Onboard logic synthesizes PXIe_SYNC100 from these two signals with the timing relationship as shown in the following figure.

This architecture has the advantage that PXI_CLK10 and PXIe_CLK100 are always sourced from the same reference oscillator, and therefore it is impossible to lose PXI_CLK10 or PXIe_CLK100 by disconnecting a reference provided on any of the supported inputs. For the same reason, it is also impossible for a runt pulse or glitch to occur on these lines as references are switched in and out, protecting the integrity of digital circuitry operating on these clocks.

A feature of this architecture is that the phase noise performance of PXI_CLK10 and PXIe_CLK100 is fixed beyond the bandwidth of the PLL loop on the backplane, regardless of the quality of reference used. This is advantageous if a reference with poor phase noise performance is used, but it also means that supplying a high end, low phase noise reference will not greatly improve PXI_CLK10 or PXIe_CLK100.