By default, a copy of the backplane’s PXI_CLK10 is exported to the 10 MHz REF OUT SMA connector as well as the Trig Port 1/10 MHz REF OUT port on the rear of the chassis. Independent buffers drive these clocks. Refer to the PXIe-1095 Specifications for the rear SMA connector 10 MHz REF OUT signal specification information. This feature is available only with the Timing and Synchronization upgrade.

On a chassis with an OCXO, you also can select the OCXO as the source for the 10 MHz REF OUT signals. One application where this is useful is when you want multiple chassis to share the same timebase and have the same phase offset. In this application, select a chassis with an OCXO to be the master timebase for the system. On this master chassis, select the OCXO as the source for the 10 MHz REF OUT port. Connect the master chassis 10 MHz REF OUT port to a clock splitter, then route the clock to each chassis’ 10 MHz REF IN port (including back to the master chassis). If you use matched-length cables, each chassis in the system is nominally matched in phase.