PCI-5421 Specifications
- Updated2025-02-25
- 23 minute(s) read
PCI-5421 Specifications
Definitions
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.
Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
- Typical specifications describe the performance met by a majority of models.
- Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.
Specifications are Nominal unless otherwise noted.
Conditions
Specifications are valid under the following conditions unless otherwise noted:
- Ambient temperature range of 0 °C to 55 °C
- Analog filter enabled
- Interpolation set to maximum allowed factor for a given sample rate
- Signals terminated with 50 Ω
- Direct path set to 1 Vpk-pk
- Low-gain amplifier path set to 2 Vpk-pk
- High-gain amplifier path set to 12 Vpk-pk
- Sample Clock set to 100 MS/s
Typical specifications are valid under the following conditions unless otherwise noted:
- Ambient temperature range of 23 ±5 °C
PCI-5421 Pinout
Use the pinout to connect to terminals on the PCI-5421.
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Signal Name | Type | Description |
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D<0..15> | Output | Digital pattern outputs. The 16-bit digital representation of the analog waveform is available on these output pins as digital pattern outputs. This data is available directly from the memory after several Sample clock pipeline delays. The digital pattern outputs are standard LVDS output levels. All data bits change on the falling edge of the DDC CLK OUT. |
DDC CLK IN | Input | These lines are used as a source for an external Sample clock. You can feed a LVDS level clock to this line with a maximum frequency of the signal generator. |
DDC CLK OUT | Output | The Sample clock is always routed to the DDC CLK OUT line of the DDC front panel connector when the digital pattern is enabled. |
Ground | — | Digital ground. |
PFI<2..3> (Inputs) | Input | These PFI lines can accept a trigger from an external source that can start or step through waveform generation. You can select this functionality on the NI 5421 through the software. |
PFI<4:5> | Output | These PFI lines can route out a signal from Marker events or the Out Start trigger. |
Reserved | — | Reserved for future use. Do not connect signals to this line. |
CH 0 Analog Output
Number of channels | 1 |
Connector type | SMB jack |
Output Voltage
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DAC resolution | 16 bits |
Amplitude and Offset
Path | Load | Amplitude (V pk-pk) | |
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Minimum | Maximum | ||
Direct | 50 Ω | 0.707 | 1.00 |
1 kΩ | 1.35 | 1.91 | |
Open | 1.41 | 2.00 | |
Low-gain amplifier | 50 Ω | 0.00564 | 2.00 |
1 kΩ | 0.0107 | 3.81 | |
Open | 0.0113 | 4.00 | |
High-gain amplifier | 50 Ω | 0.0338 | 12.0 |
1 kΩ | 0.0644 | 22.9 | |
Open | 0.0676 | 24.0 |
Accuracy
Path | DC Accuracy | |
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±10 °C of Self-Calibration Temperature | 0 °C to 55 °C | |
Low-gain amplifier | ±0.2% of Amplitude Range ± 0.05% of Offset ± 500 µV | ±0.4% of Amplitude Range ± 0.05% of Offset ± 1 mV |
High-gain amplifier | ||
Path | Gain Accuracy | |
±10 °C of Self-Calibration Temperature | 0 °C to 55 °C | |
Direct | ±0.2% Amplitude Range | ±0.4% Amplitude Range |
Output
Output impedance | Software-selectable: 50 Ω or 75 Ω, nominal |
Load impedance compensation | Output amplitude is compensated for user-specified load impedances |
Output coupling | DC |
Output enable | Software-selectable[8]8 When the output path is disabled, CH 0 is terminated to ground with a 1 W resistor with a value equal to the selected output impedance. |
Maximum output overload | CH 0 can be connected to a 50 Ω, ±12 V (±8 V for the direct path) source without sustaining any damage.[9]9 No damage occurs if CH 0 is shorted to ground indefinitely. |
Waveform summing | Supported[10]10 The output terminals of multiple PCI-5421 waveform generators can be connected directly together. |
Frequency and Transient Response
43 MHz | |||||||||||||||||||||||||||
Digital interpolation filter12 The digital filter is not available for use for Sample Clock rates below 10 MS/s. Refer to Effective Sample Rate for more information about the effect of interpolation on sample rates.[12] | Software-selectable: Finite impulse response (FIR) filter. Available interpolation factors are 2, 4, or 8. | ||||||||||||||||||||||||||
Analog filter13 Available on low-gain amplifier and high-gain amplifier paths.[13] | Software-selectable: 7-pole elliptical filter | ||||||||||||||||||||||||||
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Suggested Maximum Frequencies for Common Functions
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Spectral Characteristics
Frequency | SFDR with Harmonics (dB), Typical | ||
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Direct Path | Low-Gain Amplifier Path | High-Gain Amplifier Path | |
1 MHz | 70 | 65 | 66 |
5 MHz | 58 | ||
10 MHz | 52 | ||
20 MHz | 63 | 64 | 49 |
30 MHz | 57 | 60 | 43 |
40 MHz | 48 | 53 | 39 |
50 MHz | — | ||
60 MHz | 47 | 52 | |
70 MHz | |||
80 MHz | 41 |
Frequency | SFDR without Harmonics (dB), Typical | ||
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Direct Path | Low-Gain Amplifier Path | High-Gain Amplifier Path | |
1 MHz | 84 | 79 | 76 |
5 MHz | |||
10 MHz | 79 | ||
20 MHz | |||
30 MHz | 72 | 70 | 67 |
40 MHz | 47 | 57 | 54 |
50 MHz | 52 | — | |
60 MHz | 46 | 51 | |
70 MHz | |||
80 MHz | 40 |
Amplitude Range | Average Noise Density, Typical | |||
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dBm/Hz | dBFS/Hz | ||
1.00 V pk-pk | 4.0 dBm | 19.9 | -141 | -145 |
Amplitude Range | Average Noise Density, Typical | |||
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dBm/Hz | dBFS/Hz | ||
0.06 V pk-pk | -20.5 dBm | 1.3 | -148 | -144 |
0.10 V pk-pk | -16.0 dBm | 2.2 | ||
0.40 V pk-pk | -4.0 dBm | 8.9 | ||
1.00 V pk-pk | 4.0 dBm | 22.3 | -140 | |
2.00 V pk-pk | 10.0 dBm | 44.6 | -134 |
Amplitude Range | Average Noise Density, Typical | |||
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dBm/Hz | dBFS/Hz | ||
4.00 V pk-pk | 16.0 dBm | 93.8 | -128 | -144 |
12.00 V pk-pk | 25.6 dBm | 281.5 | -118 |
Signal to Noise and Distortion (SINAD)[19]19 Amplitude -1 decibel full scale (dBFS). Measured from DC to 50 MHz. SINAD at low amplitudes is limited by a -148 dBm/Hz noise floor.
All values are typical.
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Spurious-Free Dynamic Range (SFDR)
All values are typical and include aliased harmonics. Dynamic range is defined as the difference between the carrier level and the largest spur.
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Total Harmonic Distortion (THD)
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Average Noise Density[23]23 Average noise density at small amplitudes is limited by a -148 dBm/Hz noise floor.
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Intermodulation Distortion (IMD)[24]24 Each tone is -7 dBFS.
All values are typical.
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Spectrum Performance
The noise floor in the following figures is limited by the measurement device. Refer to Average Noise Density for more information about this limit.
Sample Clock
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Sample Rate Range and Resolution
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Effective Sample Rate
(Interpolation factor) * (Sample rate) = Effective sample rate | ||
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Interpolation factor | Sample rate | Effective sample rate |
1 (Off) | 10 S/s to 105 MS/s | 10 S/s to 105 MS/s |
2 | 12.5 MS/s to 105 MS/s | 25 MS/s to 210 MS/s |
4 | 10 MS/s to 100 MS/s | 40 MS/s to 400 MS/s |
8 | 10 MS/s to 50 MS/s | 80 MS/s to 400 MS/s |
Sample Clock Delay Range and Resolution
Sample Clock Source | Delay Adjustment Range |
---|---|
Divide-by-N | ±1 Sample Clock period |
High-Resolution | |
CLK IN | 0 ns to 7.6 ns |
DDC CLK IN | |
PXI Star Trigger | |
PXI_Trig <0..7> |
Sample Clock Source | Delay Adjustment Resolution |
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Divide-by-N | <10 ps |
High-Resolution | Sample Clock period/16,384 |
CLK IN | <15 ps |
DDC CLK IN | |
PXI Star Trigger | |
PXI_Trig <0..7> |
System Phase Noise and Jitter (10 MHz Carrier)
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Sample Clock Exporting
Destinations28 Exported Sample Clocks can be divided by integer K (1 ≤ K ≤ 4,194,304).[28] | PFI <0..1> (SMB front panel connectors) DDC CLK OUT (DIGITAL DATA & CONTROL front panel connector) RTSI<0..6> | ||||||||
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Onboard Clock (Internal VCXO)
Source | Internal Sample Clocks can either be locked to a Reference Clock using a phase-locked loop or derived from the onboard VCXO frequency reference. |
Frequency accuracy | ±25 ppm |
Phase-Locked Loop (PLL) Reference Clock
Sources[29]29 The PLL Reference Clock provides the reference frequency for the PLL. | RTSI_7 (RTSI_CLK) CLK IN (SMB front panel connector) |
Frequency accuracy | When using the PLL, the frequency accuracy of the PCI-5421 is solely dependent on the frequency accuracy of the PLL Reference Clock source. |
Lock time | 200 ms, maximum 70 ms, typical |
Frequency range[30]30 The PLL Reference Clock frequency must be accurate to ±50 ppm. | 5 MHz to 20 MHz in increments of 1 MHz[31]31 The default is 10 MHz. |
Duty cycle range | 40% to 60% |
Destinations | PFI <0..1> (SMB front panel connectors) RTSI<0..6> |
CLK IN
Connector type | SMB jack | ||||||||
Direction | Input | ||||||||
Destinations | Sample Clock PLL Reference Clock | ||||||||
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Maximum input overload | ±10 V | ||||||||
Input impedance | 50 Ω | ||||||||
Input coupling | AC |
PFI 0 and PFI 1
Connector type | SMB jack (x2) | ||||||||||||||||||||||||||
Direction | Bidirectional | ||||||||||||||||||||||||||
Frequency range | DC to 105 MHz | ||||||||||||||||||||||||||
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DIGITAL DATA & CONTROL (DDC)
Connector type | 68-pin VHDCI female receptacle |
Number of data output signals | 16 |
Control signals | DDC CLK OUT (clock output) DDC CLK IN (clock input) PFI 2 (input) PFI 3 (input) PFI 4 (output) PFI 5 (output) |
Ground | 23 pins |
Output Signals (Data Outputs, DDC CLK OUT, and PFI <4..5>)
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Output skew[35]35 Skew between any two output signals on the DIGITAL DATA & CONTROL (DDC) front panel connector. | 1 ns, typical 2 ns, maximum | ||||||||||||
Output enable/disable | Controlled through the software on all data output signals and control signals collectively. When disabled, the output signals go to a high-impedance state. | ||||||||||||
Maximum output overload | -0.3 V to +3.9 V |
Input Signals (DDC CLK IN and PFI <2..3>)
Signal type | Low-voltage differential signal (LVDS) |
Input differential impedance | 100 Ω |
Maximum output overload | -0.3 V to +3.9 V |
Differential input voltage | 0.1 V, minimum 0.5 V, maximum |
Input common mode voltage | 0.2 V, minimum 2.2 V, maximum |
DDC CLK OUT
Clocking format | Data outputs and markers change on the falling edge of DDC CLK OUT. |
Frequency range | Refer to the Sample Clock section for more information. |
Duty cycle | 40% to 60% |
Jitter | 40 ps rms |
DDC CLK IN
Clocking format | DDC data output signals change on the rising edge of DDC CLK IN. |
Frequency range | 10 Hz to 105 MHz |
Input duty cycle tolerance | 40% to 60% |
Input jitter tolerances | 300 ps pk-pk of cycle-cycle jitter 1 ns rms of period jitter |
Start Trigger
Sources | PFI<0..1> (SMB front panel connectors) PFI<2..3> (DIGITAL DATA & CONTROL front panel connector) RTSI<0..7> Software (use node or function call) Immediate (does not wait for a trigger). The default is Immediate. | ||||||||||
Modes | Single Continuous Stepped Burst | ||||||||||
Edge detection | Rising | ||||||||||
Minimum pulse width | 25 ns
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Delay from Start Trigger to DDC output | 40 Sample Clock periods + 110 ns | ||||||||||
Exported trigger destinations | A signal used as a trigger can be routed out to any destination listed in the Destinations specification of the Markers section | ||||||||||
Exported trigger delay | 65 ns, typical | ||||||||||
Exported trigger pulse width | >150 ns |
Markers
Destinations | PFI <0..1> (SMB front panel connectors) PFI <4..5> (DIGITAL DATA & CONTROL front panel connector) RTSI<0..6> | ||||||
Quantity | One marker per segment | ||||||
Quantum | Marker position must be placed at an integer multiple of four samples. | ||||||
Width | >150 ns | ||||||
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Jitter | 20 ps rms |
Arbitrary Waveform Generation Mode
Memory usage | The PCI-5421 uses the Synchronization and Memory Core (SMC) technology in which waveforms and instructions share onboard memory. Parameters—such as number of segments in sequence list, maximum number of waveforms in memory, and number of samples available for waveform storage—are flexible and user-defined. | ||||||||||
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Output modes | Arbitrary waveform36 In arbitrary waveform mode, a single waveform is selected from the set of waveforms stored in onboard memory and generated.[36] Arbitrary sequence37 In arbitrary sequence mode, a sequence directs the PCI-5421 to generate a set of waveforms in a specific order. Elements of the sequence are referred to as segments. Each segment is associated with a set of instructions. The instructions identify which waveform is selected from the set of waveforms in memory, how many loops (iterations) of the waveform are generated, and at which sample in the waveform a marker output signal is sent.[37] |
Trigger Mode | Minimum Waveform Size (Samples) | ||
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Arbitrary Waveform Mode | Arbitrary Sequence Mode[38]38 The minimum waveform size is sample rate dependent in arbitrary sequence mode. | ||
At >50 MS/s | At ≤50 MS/s | ||
Single | 16 | ||
Continuous | 16 samples | 96 samples at >50 MS/s | 32 samples at ≤50 MS/s |
Stepped | |||
Burst |
Loop count | 1 to 16,777,215 Burst trigger: Unlimited |
Quantum | Waveform size must be an integer multiple of four samples. |
Memory Limits
Onboard Memory | Maximum Waveform Memory (Samples) | |
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Arbitrary Waveform Mode | Arbitrary Sequence Mode39 One or two segments in a sequence.[39] | |
8 MB standard | 4,194,176 | 4,194,120 |
32 MB option | 16,777,088 | 16,777,008 |
256 MB option | 134,217,600 | 134,217,520 |
512 MB option | 268,435,328 | 268,435,200 |
Onboard Memory | Maximum Waveforms |
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8 MB standard | 65,000 |
Burst trigger: 8,000 | |
32 MB option | 262,000 |
Burst trigger: 32,000 | |
256 MB option | 2,097,000 |
Burst trigger: 262,000 | |
512 MB option | 4,194,000 |
Burst trigger: 524,000 |
Onboard Memory | Maximum Segments in a Sequence |
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8 MB standard | 104,000 |
Burst trigger: 65,000 | |
32 MB option | 418,000 |
Burst trigger: 262,000 | |
256 MB option | 3,354,000 |
Burst trigger: 2,090,000 | |
512 MB option | 6,708,000 |
Burst trigger: 4,180,000 |
Calibration
Self-calibration | An onboard, 24-bit ADC and precision voltage reference are used to calibrate the DC gain and offset. The self-calibration is initiated by the user through the software and takes approximately 75 seconds to complete. |
External calibration | External calibration calibrates the VCXO, voltage reference, DC gain, and offset. Appropriate constants are stored in nonvolatile memory. |
Calibration interval | Specifications valid within two years of external calibration. |
Warm-up time | 15 minutes |
Power
All values are typical. Overload operation occurs when CH 0 is shorted to ground.
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Environment
Maximum altitude | 2,000 m (at 25 °C ambient temperature) |
Pollution Degree | 2 |
Indoor use only.
Operating Environment
Ambient temperature range | 0 °C to 45 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.) |
Relative humidity range | 10% to 90%, noncondensing (Tested in accordance with IEC 60068-2-56.) |
Storage Environment
Ambient temperature range | -25 °C to 85 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.) |
Relative humidity range | 5% to 95%, noncondensing (Tested in accordance with IEC 60068-2-56.) |
Shock and Vibration
Storage shock | 50 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Test profile developed in accordance with MIL-PRF-28800F.) |
Nonoperating random vibration | 5 Hz to 500 Hz, 2.4 grms (Tested in accordance with IEC 60068-2-64. Nonoperating test profile exceeds the requirements of MIL-PRF-28800F, Class 3.) |
Physical
Dimensions | 34.1 cm × 2.0 cm × 10.7 cm (13.4 in. × 0.8 in. × 4.2 in.) |
Weight | 419 g (14.8 oz) |
Compliance and Certifications
Safety Compliance Standards
This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:
- IEC 61010-1, EN 61010-1
- UL 61010-1, CSA C22.2 No. 61010-1
Electromagnetic Compatibility
- EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
- EN 55011 (CISPR 11): Group 1, Class A emissions
- EN 55022 (CISPR 22): Class A emissions
- EN 55024 (CISPR 24): Immunity
- AS/NZS CISPR 11: Group 1, Class A emissions
- AS/NZS CISPR 22: Class A emissions
- FCC 47 CFR Part 15B: Class A emissions
- ICES-001: Class A emissions
Product Certifications and Declarations
Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for NI products, visit ni.com/product-certifications, search by model number, and click the appropriate link.
Environmental Management
NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.
For additional environmental information, refer to the Engineering a Healthy Planet web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.
EU and UK Customers
电子信息产品污染控制管理办法(中国RoHS)
1 When the main output path is selected, either the low-gain amplifier or the high-gain amplifier is used, depending on the value of the Gain property or NIFGEN_ATTR_GAIN attribute.
2 The direct path is optimized for intermediate frequency (IF) applications.
3 Amplitude values assume the full scale of the DAC is utilized. If an amplitude smaller than the minimum value is desired, then waveforms less than full scale of the DAC can be used. NI-FGEN compensates for user-specified resistive loads.
4 Offset range is not available on the direct path.
5 All paths are calibrated for amplitude and gain errors. The low-gain and high-gain amplifier paths are also calibrated for offset errors. DC accuracy is calibrated into a high-impedance load. Amplitude Range is defined as two times the gain setting. For example, a DC signal with a gain of 8 has an amplitude range of 16 V. If this signal has an offset of 1.5, DC accuracy is calculated by the following equation: ±0.2% * (16 V) ± 0.05% * (1.5 V) ± 500µV = ±33.25 mV
6 Within 0 °C to 55 °C.
7 With a 50 kHz sine wave and terminated with high impedance.
8 When the output path is disabled, CH 0 is terminated to ground with a 1 W resistor with a value equal to the selected output impedance.
9 No damage occurs if CH 0 is shorted to ground indefinitely.
10 The output terminals of multiple PCI-5421 waveform generators can be connected directly together.
11 Measured at -3 dB.
12 The digital filter is not available for use for Sample Clock rates below 10 MS/s. Refer to Effective Sample Rate for more information about the effect of interpolation on sample rates.
13 Available on low-gain amplifier and high-gain amplifier paths.
14 With respect to 50 kHz.
15 Analog filter and digital interpolation filter disabled.
16 Disable the analog filter and the digital interpolation filter for square, ramp, and triangle functions. The minimum frequency is <1 mHz. The value depends on memory size and instrument configuration.
17 At amplitude of -1 dBFS and measured from DC to 100 MHz. All values include aliased harmonics. Dynamic range is defined as the difference between the carrier level and the largest spur.
18 Average noise density at small amplitudes is limited by a -148 dBm/Hz noise floor.
19 Amplitude -1 decibel full scale (dBFS). Measured from DC to 50 MHz. SINAD at low amplitudes is limited by a -148 dBm/Hz noise floor.
20 Amplitude -1 dBFS. Measured from DC to 50 MHz. Also called harmonic distortion. SFDR with harmonics at low amplitudes is limited by a -148 dBm/Hz noise floor.
21 Amplitude -1 dBFS. Measured from DC to 50 MHz. SFDR without harmonics at low amplitudes is limited by a -148 dBm/Hz noise floor.
22 Amplitude -1 dBFS. Includes the 2nd through the 6th harmonics.
23 Average noise density at small amplitudes is limited by a -148 dBm/Hz noise floor.
24 Each tone is -7 dBFS.
25 Refer to the Onboard Clock section for more information about internal clock sources.
26 Specified at two times DAC oversampling.
27 High-Resolution specifications increase as the sample rate is decreased.
28 Exported Sample Clocks can be divided by integer K (1 ≤ K ≤ 4,194,304).
29 The PLL Reference Clock provides the reference frequency for the PLL.
30 The PLL Reference Clock frequency must be accurate to ±50 ppm.
31 The default is 10 MHz.
32 Output drivers are +3.3 V TTL compatible.
33 Load of 10 pF.
34 Tested with a 100 Ω differential load, measured at the module front panel, load capacitance <10 pF, driver and receiver comply with ANSI/TIA/EIA-644.
35 Skew between any two output signals on the DIGITAL DATA & CONTROL (DDC) front panel connector.
36 In arbitrary waveform mode, a single waveform is selected from the set of waveforms stored in onboard memory and generated.
37 In arbitrary sequence mode, a sequence directs the PCI-5421 to generate a set of waveforms in a specific order. Elements of the sequence are referred to as segments. Each segment is associated with a set of instructions. The instructions identify which waveform is selected from the set of waveforms in memory, how many loops (iterations) of the waveform are generated, and at which sample in the waveform a marker output signal is sent.
38 The minimum waveform size is sample rate dependent in arbitrary sequence mode.
39 One or two segments in a sequence.
40 Waveform memory is <4,000 samples.
In This Section
- Definitions
- Conditions
- PCI-5421 Pinout
- CH 0 Analog Output
- Sample Clock
- Onboard Clock (Internal VCXO)
- Phase-Locked Loop (PLL) Reference Clock
- CLK IN
- PFI 0 and PFI 1
- DIGITAL DATA & CONTROL (DDC)
- Start Trigger
- Markers
- Arbitrary Waveform Generation Mode
- Calibration
- Power
- Environment
- Physical
- Compliance and Certifications