NI-TClk Synchronization Help

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NI-TClk Synchronization in Multiple PXI Chassis

NI-TClk Synchronization in Multiple PXI Chassis

If the devices are in multiple PXI chassis, the Sync Pulse signal is not automatically routed. Ensure that you configure the system such that the same clock source drives all the PXI_CLK10 signals in all the chassis.

Note  To minimize phase differences between the chassis, use matched-length cables to drive the PXI_CLK10 signal to different chassis.

Routing the Triggers

When you synchronize several NI modular instruments in multiple PXI chassis with homogeneous or heterogeneous triggers, use the instrument driver VIs or functions and the following TClk VIs or functions to route the triggers so that the triggers can be shared.

LabVIEW VI C Function
niTClk Synchronize VI niTClk_Synchronize
niTClk Initiate VI niTClk_Initiate
(optional)
niTClk Is Done VI
or
niTClk Wait Until Done VI
(optional)
niTClk_IsDone
or
niTClk_WaitUntilDone
N/A niTClk_GetExtendedErrorInfo

To specify how the triggers must be shared between the devices, use the NI-TClk properties or attributes listed in the following table.


LabVIEW Property C Attribute
Start Trigger Master Session NITCLK_ATTR_START_TRIGGER_MASTER_SESSION
Reference Trigger Master Session NITCLK_ATTR_REF_TRIGGER_MASTER_SESSION
Script Trigger Master Session NITCLK_ATTR_SCRIPT_TRIGGER_MASTER_SESSION
Pause Trigger Master Session NITCLK_ATTR_PAUSE_TRIGGER_MASTER_SESSION

When the Sample Clock rates, Sample Clock timebase rates, and/or the sample counts are different in acquisition sessions sharing the Reference Trigger, you should also set the holdoff attributes for the Reference Trigger master using the instrument driver.


Routing the Sync Pulse Signal

To route the Sync Pulse signal in a multiple chassis system, use PXI synchronization modules, such as NI PXI-6653, in each chassis. Install these modules in the System Timing Slot to supply a common 10 MHz clock signal to all the chassis.

To specify how to route the Sync Pulse signal, use the NI-TClk properties or attributes listed in the following table.

LabVIEW Property C Attribute
Sync Pulse Source NITCLK_ATTR_SYNC_PULSE_SOURCE
Export Sync Pulse Output Terminal NITCLK_ATTR_EXPORTED_SYNC_PULSE_OUTPUT_TERMINAL

Example

If chassis A contains the device that exports the Sync Pulse signal, and chassis A is connected to chassis B and chassis C through the PXI synchronization modules and cables, then use the following signal routing.

  1. Route the Sync Pulse signal from the device that exports this signal to the PXI synchronization module, using a PXI trigger line (line X).
  2. Resynchronize to PXI_CLK10 in the PXI synchronization module. Route the Sync Pulse signal to the following locations.
    1. Another PXI trigger line (line Y) in the same chassis (where line Y is not the same PXI trigger line as line X)
    2. The PXI synchronization modules in chassis B and chassis C
  3. Program the devices in chassis A to receive the signal from the PXI trigger line Y.
  4. Route the Sync Pulse signal, without resynchronizing, from the PXI synchronization module on chassis B and chassis C to the PXI trigger line Y on chassis B and chassis C.
  5. Program the devices in chassis B and chassis C to receive the Sync Pulse signal from the PXI trigger line Y.

If the PXI trigger line Y is not available in chassis B and chassis C, use any other available trigger line. Use the same trigger line in all the chassis to simplify programming.

Keep the total signal propagation delay to less than 100 ns, for all the cables and the PXI synchronization modules.

Contact National Instruments technical support for more information about synchronizing multiple PXI chassis. Refer to Configuring PXI Chassis with Multiple Bus Segments (18-Slot Chassis) for more information about the 18-slot PXI chassis.

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