Reference Clock/Phase-Lock Loop

The reference clock is used in the phase-locked loop (PLL) circuit of a digitizer to synchronize the internal oscillator to the reference clock. The frequency stability of the internal oscillator matches that of the PLL reference clock when the two are phase locked. In turn, phase locking synchronizes clocks of multiple devices that are phase locked to the same reference clock. The most common frequency for a reference clock is 10 MHz because a clock of that frequency can generally be shared over a cable without much attenuation or loss. However, the frequency range of reference clocks can vary anywhere from 1 MHz to 20 MHz. Refer to the Devices section of this help file to determine what your device supports. The following figure shows a block diagram of a basic PLL.

The operation of this circuit is typical of all PLLs. A PLL is a feedback control system that controls the frequency and phase of a voltage controlled oscillator (VCO). The input signal is applied to a phase detector. The output of the VCO connects to the other input. As shown in the previous diagram, the frequencies of both signals are the same. The output of the phase detector develops a voltage proportional to the phase difference between the two input signals. The lowpass filter receives this signal from the phase detector. The lowpass filter determines the dynamic characteristics of the PLL. The filtered signal controls the VCO.