Front Panel and Connector Pinouts

The NI 6589 provides one PFI signal and one clock signal through the two SMA connectors on the device front panel. Additionally, the NI 6589 provides sixteen LVDS signals, four LVDS PFI signals, three single-ended PFI signals, and an LVDS clock out signal on the Digital Data & Control (DDC) connector. The following figure shows the front panel connector and signal descriptions for the NI 6589.

Figure 3. NI 6589 Front Panel and Connector Pinout


Caution To avoid permanent damage to the NI 6589, disconnect all signals connected to the NI 6589 before powering down the module, and connect signals only after the adapter module has been powered on by the FlexRIO FPGA module or Controller for FlexRIO.
Caution Connections that exceed any of the maximum ratings of any connector on the NI 6589 can damage the device and the chassis. NI is not liable for any damage resulting from such connections.
Note If you design a custom cabling solution with the Infiniband connector (779157-01) and the SHB12X-B12X LVDS shielded cable (192344-01), the NI 6589 pinout is reversed at the end connector. For example, the signal shown on pin 1 maps to pin 73 in the pinout at the end connector.

The following table contains SMA pin location information and signal information for the NI 6589. The signal names listed in this table refer to the signals shown in the front panel pinout.

Table 2. SMA Connector Names and Descriptions
Signal Name Connector Signal Type Signal Description
PFI 0 PFI 0 Control Bidirectional single-ended terminal for channel PFI 0.
CLOCK IN CLOCK IN Clock External single-ended clock input terminal.

The following table contains DDC pin location information for the NI 6589. The signal names listed in this table refer to the signals shown in the front panel pinout.

Table 3. NI 6589 DDC Connector Names and Descriptions
Signal Name Pin(s) Signal Type Signal Description
DDC CLK OUT+ 65 Control Positive terminal for the LVDS exported Sample Clock.
DDC CLK OUT- 66 Control Negative terminal for the LVDS exported Sample Clock.
STROBE+ 62 Control Positive differential terminal for the external Sample Clock source that can be used for synchronous dynamic acquisition.
STROBE- 63 Control Negative differential terminal for the external Sample Clock source that can be used for synchronous dynamic acquisition.
DIO<0..15>+ 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59 Data Positive differential terminal for the bidirectional digitial I/O data channels 0 through 15.
DIO<0..15>- 15, 18, 21, 24, 27, 30, 33, 36, 39, 42, 45, 48, 51, 54, 57, 60 Data Negative differential terminal for the bidirectional digitial I/O data channels 0 through 15.
PFI <1..4>+ 2, 5, 8, 11 Control Positive differential terminals for bidirectional PFI channels 1 through 4.
PFI <1..4>- 3, 6, 9, 12 Control Negative differential terminals for bidirectional PFI channels 1 through 4.
SE_PFI<1..3> 68, 71, 72 Control Single-ended terminals for bidirectional PFI channels 1 through 3.
GND 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 42, 46, 49, 52, 55, 58, 69 Ground Ground reference for signals.