The NI 6587 ships with socketed CLIP that adds module I/O to the LabVIEW project. The NI-developed are as follows:

NI 6589 Basic Connector CLIP—

Provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels, where the channels are grouped by connector. You can access the LVDS data and direction lines using a U16 data type in which each bit position corresponds to an individual channel. You can access the LVDS PFI lines and the single-ended PFI lines using a Boolean control.

This CLIP provides access to the following signals.

• Sixteen bidirectional data LVDS lines
• Four LVDS PFI lines
• One LVDS STROBE line
• One LVDS clock output signal
• Four single-ended PFI lines
• One single-ended clock input signal

NI 6589 Serdes Channel CLIP—

Provides read/write access to all LVDS and single-ended channels using a channel-based interface. You can access the LVDS data and PFI channels using a U16 data type in which the top six bits are unused. Each LVDS line, PFI line, and clock output is connected to an OSERDES or ISERDES block that serializes or deserializes, respectively, the signal by a factor of 10 by default. During acquisition, the NI 6589 reads or writes ten bits of data per channel to or from the ISERDES or OSERDES blocks. All OSERDES and ISERDES blocks are set to double data rate (DDR) mode. The SERDES will serialize or deserialize the LVDS data in bit order from MSB to LSB.

This CLIP provides access to the following signals.

• Sixteen bidirectional data LVDS lines
• Four LVDS PFI lines
• One LVDS STROBE line
• One LVDS clock output signal
• Four single-ended PFI lines
• One single-ended clock input signal

NI 6589 Serdes Connector CLIP—

Provides read/write access to all LVDS and single-ended channels, where the channels are grouped by connector. This CLIP conveys parallel data at high speeds. You can access the LVDS data and direction lines using a U16 data type, you can access the LVDS PFI lines using a U8 data type, and you can access the single-ended PFI lines using a Boolean control. In the U8 data type, the top four bits are unused. Each LVDS line, PFI line, and clock output is connected to an OSERDES or ISERDES block that serializes or deserializes, respectively, the signal by a factor of six by default. Therefore, with every regional clock cycle, the NI 6589 reads or writes six samples to or from the ISERDES or OSERDES blocks. All OSERDES and ISERDES blocks are set to double data rate (DDR) mode. The SERDES will serialize or deserialize the LVDS data in bit order from MSB to LSB.

This CLIP provides access to the following signals.

• Sixteen bidirectional data LVDS lines
• Four LVDS PFI lines
• One LVDS STROBE line
• One LVDS clock output signal
• Four single-ended PFI lines
• One single-ended clock input signal

The following table lists the NI 6589 SMA connector signals and corresponding FlexRIO FPGA module signals necessary for designing custom component-level IP (CLIP).

The following table lists the NI 6589 DDC connector signals and corresponding FlexRIO FPGA module signals necessary for designing custom component-level IP (CLIP). The _CC suffix on signals identifies channels that can receive a regional clock.