General

Right-click the base clock in the Project Explorer window and select Properties from the shortcut menu to display this dialog box.

Use the FPGA Base Clock Properties dialog box to configure an FPGA base clock associated with an FPGA target.

The options available in this dialog box vary according to FPGA target and clock.

This dialog box might include the following components:


icon

Inputs/Outputs

  • cdlrn.png page sync rendezvous —

    rendezvous is a reference to an existing or newly created rendezvous.

  • cerrcodeclst.png error in (no error) —

    The error in cluster can accept error information wired from VIs previously called. Use this information to decide if any functionality should be bypassed in the event of errors from other VIs. The pop-up option Explain Error (or Explain Warning) gives more information about the error displayed.