Top-Level Clock

Right-click an FPGA target in the Project Explorer window and select Properties from the shortcut menu to display the FPGA Target Properties dialog box. Select Top-Level Clock from the Category list to display this page.

Use this page to set the top-level clock of the FPGA target. Supported top-level clocks vary according to FPGA target.

This page includes the following components:


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Inputs/Outputs

  • cdlrn.png page sync rendezvous —

    rendezvous is a reference to an existing or newly created rendezvous.

  • cerrcodeclst.png error in (no error) —

    The error in cluster can accept error information wired from VIs previously called. Use this information to decide if any functionality should be bypassed in the event of errors from other VIs. The pop-up option Explain Error (or Explain Warning) gives more information about the error displayed.