Using I/O, Clocks, Register Items, Memory Items, FIFOs, and Handshake Items in SubVIs

Use name controls to create subVIs that can be reused with different I/O, clock, register, memory, FIFO, or handshake resources. You can use name controls only in reentrant FPGA subVIs.

Complete the following steps to enable a subVI to accept an FPGA I/O, clock, register, memory, or FIFO resource.

1. Place an FPGA I/O Node, Register Method Node, Memory Method Node, FIFO Method Node, or Handshake Method Node on the block diagram of your subVI. To select an FPGA clock, place a single-cycle Timed Loop on the block diagram of your subVI.
2. Right-click the FPGA I/O In, Register In, Memory In, FIFO In, Handshake In, or Source Name input terminal and select Create»Control.
3. Assign the I/O, register, memory, FIFO, handshake, or clock control to a connector pane terminal of the subVI.

Passing I/O, Clocks, Register Items, Memory Items, FIFOs, or Handshake Items to a SubVI

The following block diagram shows MemoryControl.vi with the memory control, Memory In, wired to a Memory Method Node.

The following block diagram shows MemoryControl.vi as the referenced subVI. Notice that the VI-Defined Memory Configuration node specifies the memory item to use in the calling VI below. This design means that if you want to execute MemoryControl.vi with a different memory item, you only have to change the item to which Memory In refers using the VI-Defined Memory Configuration node.

Restrictions on FPGA Name Controls

The following restrictions apply to FPGA I/O, cRIO I/O, memory, FIFO, handshake, and clock controls:

• You can change the value of FPGA name controls only when programming the FPGA VI. You cannot change the values while an FPGA VI runs on a development computer or when using interactive front panel communication.
• FPGA name controls are available only when programming VIs under an FPGA target. FPGA name controls are not available when programming host VIs.
• You can bundle FPGA name controls into clusters with other FPGA name controls, with occurrence refnums, and with other data types. However, you cannot have such a cluster on the front panel of the top-level FPGA VI. LabVIEW returns an error when you attempt to compile the FPGA VI.