Timing FPGA VIs with Arbitration Enabled
- Updated2023-12-13
- 2 minute(s) read
Timing FPGA VIs with Arbitration Enabled
Not all arbitration options take the same amount of time to execute. If you want accesses to multiple resources of the same type to occur simultaneously, you must choose arbitration options for each resource that take the same amount of time to execute. The following block diagram illustrates an FPGA VI that might have a timing problem depending on the arbitration options selected.
The FPGA I/O Nodes shown in the block diagram above have three arbitration options. If you choose the Always Arbitrate arbitration option, LabVIEW implements an equivalent arbiter for both DIO0 and DIO1. Both arbiters take the same amount of time to execute, so DIO0 and DIO1 output simultaneously in the first frame of the Flat Sequence structure, as long as another object elsewhere on the block diagram does not simultaneously request access to either DIO0 or DIO1.
If you choose the Arbitrate if Multiple Requestors Only arbitration option, LabVIEW implements an arbiter for DIO0 but does not implement an arbiter for DIO1. DIO0 uses an arbiter because DIO0 is accessed from two different places on the block diagram. DIO1 uses no arbiter because DIO1 is accessed only once. DIO0 takes longer to execute than DIO1, so DIO0 and DIO1 do not output simultaneously in the first frame of the Flat Sequence structure.
If you choose the Never Arbitrate arbitration option for both FPGA I/O Nodes, LabVIEW does not implement an arbiter for either DIO0 or DIO1. Therefore, DIO0 and DIO1 produce output simultaneously. This is safe because the Sequence structure ensures sequential access to DIO0 unless another object on the block diagram requests simultaneous access to DIO0.