Designing a Host VI to Read Data in DMA Applications

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Updated2023-12-13
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Designing a host VI to read data from a DMA channel is an important part of implementing a DMA application.

Note The designs discussed in this topic apply for applications that transfer data from an FPGA target to a host computer.

Choosing a Design

The following table summarizes some useful designs:


Use Case	Design	Advantages	Disadvantages
An application in which one or more of the following situations occur: The FPGA acquires data at an unknown rate. You do not know when data acquisition will start; for example, a hardware device triggers acquisition at an unknown or irregular interval. You must read all data from the buffer before executing any other tasks.	Blocking	Simplest programming design. Data throughput is higher than with either polling design.	The host VI can read either the entire Number of Elements or nothing. You wire this number to the FIFO.Read method of the Invoke Method function. For some targets, the host VI cannot execute any other tasks while waiting for the Number of Elements to become available. For these targets, if you are running the host VI on a real-time system, the real-time system may become temporarily inaccessible from the host desktop system. Refer to your target hardware documentation for more information about DMA restrictions.
A data logging application where the FPGA acquires data at a known rate but the host computer reads data at an unknown or irregular rate.	Polling a variable number of elements	The host VI can read any number of elements as soon as the data becomes available to read.	Compared with the blocking design: Reading data takes more time. Data throughput might be lower.
An application that requires a fixed, known amount of data to be read before continuing but must complete other tasks while waiting for data to become available. For example, consider an application that processes 1024 elements as a single frame of data but also must send commands to another target. The fixed-polling design reads data from the buffer when data is available but sends the necessary commands when it is not. This design also is useful if the FPGA acquires data at an unknown or irregular rate.	Polling a fixed number of elements	The host VI can execute other sequential tasks while waiting for data to become available.	The host VI can read either the entire Number of Elements or nothing. You wire this number to the FIFO.Read method of the Invoke Method function. Compared with the blocking design: Reading data takes more time. Data throughput might be lower.

Programming the Host VI

Consider the following FPGA VI:

1378

This VI represents data acquisition by measuring the temperature of an FPGA device at a pre-determined rate and writing this temperature value to an FPGA DMA buffer. The following sections show example host VIs that read this data.