Controlling the FPGA VI Execution Rate
- Updated2023-12-13
- 2 minute(s) read
Controlling the FPGA VI Execution Rate
For some FPGA targets, you can configure the FPGA base clock and set it as the top-level clock in the project to control execution rates. You also can use a derived clock to circumvent base clock configuration restrictions. Different FPGA targets support different FPGA-derived clocks. For information on allowed base clock configurations for different FPGA targets, refer to the specific FPGA target hardware documentation.
Complete the following steps to create an FPGA-derived clock to control the execution rate of items on the block diagram.
- Create a new project or open an existing project.
- Add an FPGA target to the project.
- Create an FPGA-derived clock to run at the execution rate you want.
- Set the FPGA-derived clock as the top level clock.