Not Exclusive Or Function

Computes the logical negation of the logical exclusive or (XOR) of the inputs. Both inputs must be Boolean values, numeric values, or error clusters. If both inputs are TRUE or both inputs are FALSE, the function returns TRUE. Otherwise, it returns FALSE.

Note This function performs bitwise operations on numeric inputs.

The connector pane displays the default data types for this polymorphic function.


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Inputs/Outputs

  • cbool.png x

    x must be a Boolean value or a number. x can be a scalar, array or cluster of numbers or Boolean values, array of clusters of numbers or Boolean values, and so on. If x is an error cluster, only the status parameter of the error cluster passes to the input terminal.

  • cbool.png y

    y must be a Boolean value or a number. y can be a scalar, array or cluster of numbers or Boolean values, arrays of clusters of numbers or Boolean values, and so on. If y is an error cluster, only the status parameter of the error cluster passes to the input terminal.

  • ibool.png .not. (x .xor. y)?

    .not. (x .xor. y)? is the logical negation of the logical exclusive or (XOR) of x and y.

  • Not Exclusive Or Truth Table>

    xy.not. (x .xor. y)?
    TTT
    TFF
    FTF
    FFT

    FPGA Module Details

    The following details apply when you use this object in an FPGA VI.

    Note The following details are subject to change with each version of the LabVIEW FPGA Module.
    Single-Cycle Timed Loop Supported.
    Usage For maximum time and resource efficiency, use Boolean functions inside a single-cycle Timed Loop.
    Timing

    Inside single-cycle Timed Loop--When you use Boolean functions inside a single-cycle Timed Loop, each Boolean operation adds slightly to the combinatorial logic delay of the single-cycle Timed Loop.

    Outside single-cycle Timed Loop--When you use Boolean functions outside a single-cycle Timed Loop, each Boolean operation requires one clock cycle.

    Resources Boolean functions consume significant FPGA resources only when you wire a large array to the input. Consider limiting arrays to conserve FPGA resources.

    Examples

    Refer to the following example files included with LabVIEW.

    • labview\examples\Booleans\Boolean Functions.vi